Abstract: A sense current generation apparatus constituted of: a main electronically controlled switch arranged to provide a current path for an input current; a sense electronically controlled switch arranged to generate a sense current; a voltage matching circuit arranged to adjust the voltage across the first and second terminals of the sense switch to equal the voltage across the first and second terminals of the main switch, within a predetermined maximum error voltage, such that the sense current is representative of the input current; and a voltage governor arranged to: receive an indication of the voltage across the first and second terminals of the main switch; and responsive to the received voltage indication, adjust the control voltage of the main switch such that the absolute value of the voltage across the terminals thereof is maintained above a predetermined voltage threshold greater than a boundary of the error range.

Abstract: A multiplexed sigma delta modulator constituted of: a control circuitry; a multiplexer responsive to the control circuitry and arranged to receive a plurality of input signals; a comparing circuit, a first input of the comparing circuit coupled to the output of the multiplexer; an integrator, the input of the integrator coupled to the output of the comparing circuit; a latched comparing circuit, one input of the latched comparing circuit coupled to the output of the integrator; a plurality of storage elements, each associated with one of the plurality of inputs; and a feedback circuit arranged to feedback the output of the latched comparing circuit to the second input of the comparing circuit, wherein the control circuitry is further arranged to store the charge of an element of the integrator on the associated storage element when the associated signal is not passed by the multiplexer to the output of the multiplexer.

Abstract: A port current control arrangement, constituted of: a current source arranged to generate a reference current or a predetermined value; an on-chip reference resistor, the generated reference current arranged to produce a reference voltage across the on-chip reference resistor; an on-chip sense resistor, a port current arranged to flow through the on-chip sense resistor and produce a sense voltage across the on-chip sense resistor, wherein the resistance of the on-chip sense resistor exhibits a predetermined relationship with the resistance of the first on-chip reference resistor; and a current control circuit, a first input of the current control circuit arranged to receive the produced reference voltage and a second input of the current control circuit arranged to receive the sense voltage, wherein the current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage.

Abstract: An input circuitry for an ADC constituted of: a first resistor coupled to an input of the ADC; a second resistor coupled to the input of the ADC and arranged to provide a current path; an electronically controlled switch coupled to the first resistor and arranged to provide a parallel current path through the first resistor; and a control circuitry; wherein the control circuitry is arranged to operate in a high current mode in the event that the input current exhibits an intensity within a first predetermined range and is arranged to operate in a low current mode in the event that the input current exhibits an intensity within a second predetermined range, different than the first predetermined range, wherein, in the high current mode the control circuitry is arranged to close the electronically controlled switch and in the low current mode is arranged to open the electronically controlled switch.

Abstract: A dual port pass through midspan constituted of: a first port arranged for connection to a first data terminal equipment over a first data communication cabling; a second port arranged for connection to a second data terminal equipment over a second data communication cabling; a first power sourcing equipment arranged to inject power on two of the 4 wire pairs of the first data communication cabling; a second power sourcing equipment arranged to inject power on two of the 4 wire pairs of the second data communication cabling; and a data pass through connection arranged to pass high speed data signals between the first port to the second port, the data pass through connection comprising a direct current blocking circuit arranged to: prevent power from the first power sourcing equipment from appearing at the second port; and prevent power from the second power sourcing equipment from appearing at the first port.

Abstract: A twin power sourcing equipment constituted of: a first power sourcing equipment; and a second power sourcing equipment arranged for connection to a powered device over respective power paths; the first and second power sourcing equipments arranged to: simultaneously perform detection of the powered device; and in the event that at least one of the first and second power sourcing equipments detects the presence of the powered device, alternately perform detection of the powered device to detect a signature impedance; and in the event that each of the alternate detection is indicative of the presence of the signature impedance, provide power to the powered device simultaneously by the first and second power sourcing equipment. Power is not provided to the powered device in the event that the simultaneous detection is indicative of the absence of the powered device on each of the first path and the second path.

Abstract: A powered device interface arranged as an interface between power received over a structured communication cabling and a powered device, the powered device interface constituted of: a class event counter; a logic circuit in communication with the class event counter; and a plurality of flag outputs each responsive to the logic circuit, each of the flag outputs associated with a predetermined powering level of a power sourcing equipment connected over the structured communication cabling, the logic circuit arranged to: output an active signal at the flag output associated with a detected powering level of the connected power sourcing equipment; and output an active signal at all other flag outputs associated with powering levels less than the detected powering level of the connected power sourcing equipment.

Abstract: A power sourcing equipment (PSE) exhibiting a low power sleep mode, the PSE constituted of: a sleep control circuitry comprising a first timer; an effective resistance threshold detector responsive to the sleep control circuitry and arranged to detect whether the effective resistance across the output port of the PSE is less than a predetermined threshold; and a detection and powering circuitry responsive to the sleep control circuitry, wherein the sleep control circuitry is arranged to load the first timer with a first predetermined time period, and at the expiration of the first predetermined time period: activate the effective resistance threshold detector for a second predetermined time period; and in the event the effective resistance threshold detector detects that the effective resistance across the output port of the PSE is less than the predetermined threshold, enable the detection and powering circuitry.

Abstract: A phase cut angle converter with range detection for a phase cut dimmer constituted of: a phase cut angle detector arranged to detect the phase cut angle presented by the phase cut dimmer blocking a portion of an alternating current mains power sine wave from reaching a power converter, and output a signal whose value is responsive to the detected phase cut angle; a storage functionality constituted of a memory in communication with the phase cut angle detector, the storage functionality arranged to detect each of a minimum value and a maximum value for the detected phase cut angle of the phase cut angle detector and store the minimum value and the maximum value on the memory; and a signal adjustment functionality arranged to convert the detected phase cut angle to a dimming signal responsive to the stored minimum value and the maximum value for the detected phase cut angle.

Abstract: A color manager for use with a luminaire constituted of a plurality of different colored light emitting diode based sub-luminaires arranged to produce a combined light. The color manager is constituted of a sampler arranged to output an electrical representation of the optical output of the luminaire, a converter coupled to the output of said sampler and operatively associated with a current selector arranged to select the driving current level of the luminaire from a plurality of current levels. The converter is arranged to convert said electrical representation to a pre-determined calorimetric system in cooperation with a calibration matrix whose values are selected responsive to the selected driving current level. The color manager further comprises a driver operatively associated with the luminaire, the converter and current selector and arranged to drive the luminaire in accordance with the driving current level as selected by the selector.

Abstract: A midspan unit arranged to supply power to a powered device over data communication cabling constituted of a signal conditioner exhibiting a transfer function with a gain of not less than ?0.4 dB as compared with: (K1*(s+R/L1+a)^m)/((s+R/L2+b)^n) over a predetermined frequency range associated with the data transmitted from the powered device. s represents 2*?*(??1)*f, wherein f represents the predetermined frequency range associated with the data terminal equipment to be powered. R represents the signal source impedance in parallel with the load termination impedance. L1 represents the effective inductance of a data transformer winding of the data transmitter of the powered device, the effective inductance determined responsive to power received by the powered device from the power sourcing equipment; and L2 represents the effective inductance of the data transformer winding of the data transmitter of the powered device expected by a receiver of the switch or hub equipment.

Abstract: A power saving arrangement for use with a phase cut dimmer, the power saving arrangement constituted of: a power converter arranged to convert a received alternating current power signal to a direct current signal; a detector arranged to detect the presence, or absence, of the phase cut dimmer blocking a portion of an alternating current mains power sine wave from reaching the power converter; and a controllable minimum holding current circuit in communication with the received alternating current power signal, the controllable minimum holding current circuit responsive to an output of the detector, wherein in the event that the detector detects the absence of the phase cut dimmer, the controllable minimum holding current circuit is disabled such that a minimum holding current is not provided.

Abstract: A solid state lighting controller arranged for use with a single stage power factor correction switched mode power supply, a light emitting diode (LED) string and a current sense element arranged to sense current through the LED string, the solid state lighting controller constituted of: a current governor in series with the LED string exhibiting a governor differential amplifier and a governor electronically controlled switch responsive to the output of the governor differential amplifier, the current governor arranged to limit current flow through the LED string responsive to a current limit reference; and a feedback circuit exhibiting an error amplifier, the feedback circuit arranged to feedback a signal to the power factor correction switched mode power supply controller whose value is a function of the difference between the current through the LED string sensed by the current sense element and a target current signal.

Abstract: A PSE configured to determine the end of the start up phase at the PD responsive to a condition of the voltage at the PSE output. In one particular embodiment, the startup phase end is determined responsive to a PSE output voltage within a predetermined range of the PSE input voltage. In another particular embodiment, the startup phase end is determined responsive to the voltage drop associated with the PSE current limiter being lower than a predetermined maximum. In yet another particular embodiment, the startup phase end is determined responsive to the absolute value of the rate of change of the PSE output voltage being lower than a predetermined value. In yet another particular embodiment, the startup phase end is determined responsive to the absolute value of the rate of change of the voltage drop associated with the PSE current limiter being lower than a predetermined value.

Abstract: A system for location identification in a local area network comprising: a current limited voltage source; a telecommunications outlet; communication cabling connecting the current limited voltage source to the telecommunications outlet; and a location identifier associated with the telecommunications outlet, the location identifier being responsive to a pre-determined voltage level from the current limited voltage source to transmit a multi-bit location data. In one embodiment the multi-bit location data is received at the power sourcing equipment and in another embodiment the multi-bit location data is received at a data terminal equipment connected to the telecommunications outlet.

Abstract: A synchronizer constituted of a first and second set of three serially coupled latches coupled to a common clocking signal, the first and the ultimate latch of the first set responsive to a first edge of a common clocking signal and the penultimate latch responsive to an opposing edge of the common clocking signal, the second set being respectively responsive to the respective complementary edges of the clocking signal; an input lead arranged to receive a signal to be synchronized, the input lead coupled to the input of the first latch of the first set and to the input of the first latch of the second set; and a filter arranged to pass the output of each of the first set and the second set responsive to the penultimate latch of the set exhibiting a consistent output for two consecutive opposing edges.

Abstract: A power over Ethernet extender arranged to detect if power is received over 2 pairs of wires or over 4 pairs of wires. If power is received over 4 pairs of wires, power is output over only 2 pairs of wires. Preferably, the power signature of the received power is further detected. If the incoming power over a first 2 pairs of wires supports in excess of 13 watts of power consumption, and power is received over 4 pairs, then the output power supports in excess of 13 watts of power consumption; and if the incoming power over a first 2 pairs of wires supports in excess of 13 watts of power consumption, and power is not received over 4 pairs, then the output power does not support in excess of 13 watts of power consumption.

Abstract: A system for powering and controlling an LED backlight, the system comprising: a control circuitry; a controllable power source responsive to the control circuitry; and a plurality of LED strings receiving power from the controllable power source, the control circuitry being operative to control the output voltage of the controllable power source responsive to a function of an electrical characteristic of at least one of the plurality of LED strings.

Abstract: An automated method of sampling an electrical condition of each of a plurality channels, the method comprising: driving each of the plurality of channels with a modulated signal; providing a settable flag associated with each of the plurality of channels; selecting one of the plurality of channels; identifying if the settable flag associated with the selected one of the plurality of channels is set; and in the event that the settable flag associated with the selected one of the plurality of channels is not set, and a function of the modulated signal of the selected one of the plurality of channels is active and stable: sampling an electrical condition of the selected one of the plurality of channels; and setting the provided settable flag associated with the selected one of the plurality of channels.

Abstract: A method of controlling a power over Ethernet system, the method comprising: sequentially powering a plurality of powered devices over communication cabling; determining a first total power consumption responsive to the powering of the plurality of powered devices; in the event that the determined first total power consumption exceeds a predetermined maximum power level, disabling power from at least one of the powered plurality of powered devices thereby reducing power consumption to less than the predetermined maximum power level; responsive to the disabling power, defining a connection power limit lower than the maximum power level by a guard band; monitoring a second total power consumption subsequent to the disabling power; and enabling power to a powered device only in the event the monitored second total power consumption is less than the connection power limit.