Abstract: Systems, apparatuses, and methods related to predictive memory management are described. Error correction operations can be performed on a memory system and can include a latency associated with performing various error correction techniques on data and the health of physical addresses used to store the data can be predicted based on that latency information. In an example, a method can include determining, by a controller, latency information corresponding to one or more error correction operations performed on data received by the controller, and assigning, based on the latency information corresponding to a health of physical address locations corresponding to the data, and taking an action involving the physical address locations based, at least in part, on the information corresponding to the health of the plurality of physical address locations corresponding to the data.

Abstract: Methods, systems, and devices for a current monitor for a memory device are described. A memory device may monitor potential degradation of memory cells on the device by monitoring the amount of current drawn by one or more memory cells. As the memory cells degrade, the current supplied to the memory cells may change (e.g., increase due to additional leakage current. The memory device may indirectly monitor changes in the current supplied to the memory cells by monitoring a voltage of a node of a transistor that controls the amount of current supplied to the array of memory cells. The voltage at the control node may be compared to a reference voltage to determine whether the two voltages differ by a threshold amount, indicating that the memory cells are drawing more current. The memory device may output a status indicator when the voltages differ, for example, by the threshold amount.

Abstract: Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines.

Abstract: Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit.

Abstract: In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method includes receiving an identifier, receiving output from a command line utility, and storing the command line utility output in a system storage at a location identified by the identifier. In one illustrative embodiment, command line utility output is stored in a system registry database. In another illustrative embodiment, command line utility output is stored in a shared system memory. The method may be stored in any media that is readable and executable by a computer system.

Abstract: Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.

Abstract: Disclosed herein are exemplary embodiments of an improved differential input buffer for receiving low power signals and associated methods. The disclosed buffer circuit comprises at least one differential amplifier for receiving as inputs an enable signal (e.g., a clock enable signal) and a reference signal, and provides a differential amplifier output representative of a comparison of the magnitude of the input signals. As improved, input buffer circuitry comprises a pull up stage to pull up the voltage of the differential amplifier output slightly higher during an output low condition. The pull up stage is preferably, but not necessarily, activated only during a problematic condition, such as when both input signals to the differential amplifier are low. By pulling up the output, the input buffer circuit enjoys improved margin, and is able to reliably signal a low power condition even when both inputs are low.

Abstract: The invention encompasses a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising Cl?, NO3? and F?. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.

Abstract: A clock generator comprising a master delay locked loop (DLL) and a slave DLL to capture a data signal. The slave DLL generates a slave output signal based on a clock signal. The master DLL receives the slave output signal and compensates variations in delays of the data and clock signals to generate a capture clock signal. When the master and slave DLLs are locked, the capture clock signal is center aligned with the data signal.

Abstract: Some synchronous semiconductor memory devices accept a command clock which is buffered and a write clock which is unbuffered. Write command are synchronized to the command clock while the associated write data is synchronized to the write clock. Due to the use of the buffer, an arbitrary phase shift can exist between the command and write clocks. The presence of the phase shift between the two clocks makes it difficult to determine when a memory device should accept write data associated a write command. A synchronous memory device in accordance with the present invention utilizes the unbuffered strobe signal which is normally tristated during writes as a flag to mark the start of write data. A preamble signal may be asserted on the strobe signal line prior to asserting the flag signal in order to simplify flag detection.

Abstract: An improved structure and method for gated lateral bipolar transistors are provided. Embodiments of the present invention capitalize on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of the transistors are biased to modify the threshold voltage of the transistor (Vt). The conductive sidewall member configuration conserves surface space and achieves a higher density of surface structures per chip. The structures offer performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: Disclosed is an improved stacked capacitor with rounded corners for increasing capacitor breakdown voltage, and a method of constructing the same. The preferred method comprises rounding corners of a container-shaped bottom electrode. In particular, sharp corners of a pre-fabricated conductive silicon container are exposed to an ammonium hydroxide/peroxide mixture. The slow etching effect of the clean rounds angled surfaces thereby minimizing the high field effects usually associated with corners and other angled surfaces. Reducing such field effects by reducing or eliminating sharp corners helps prevent breakdown of the capacitor structure dielectric. Where the conductive container includes a rough layer, such as hemispherical grained silicon, the invention provides the additional advantage of separating individual hemispherical grains, thus allowing later deposition of a uniformly thick dielectric layer.