Patents Assigned to Mitsubishi Denki Kabushika Kaisha
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Patent number: 7813703Abstract: A communication system includes mobile stations carrying out transmission at report cycles selected from a group consisting of 0, 1 and other integers without having a relation of a multiple and including a lot of prime numbers.Type: GrantFiled: March 3, 2006Date of Patent: October 12, 2010Assignee: Mitsubishi Denki Kabushika KaishaInventor: Kazuhito Niwano
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Patent number: 7271517Abstract: A three-phase alternating current generator includes a bowl-shaped flywheel, sixteen permanent magnets provided on an inner circumferential surface of the flywheel, and a stator located in the flywheel. Further, The stator is composed of twelve teeth provided opposite to the permanent magnets and of coils each being continuously wound around every three teeth among the teeth for generating electric power by an electromagnetic induction effect with the magnets.Type: GrantFiled: May 6, 2003Date of Patent: September 18, 2007Assignee: Mitsubishi Denki Kabushika KaishaInventors: Fumito Uemura, Shinji Baba, Hirohisa Yokota
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Publication number: 20050156944Abstract: A method of changing edge sharpness of an input image being formed from input pixels having intensity levels, the method including detecting pixel-to-pixel variations in the intensity levels in at least one direction in the input image, thereby generating local pixel variation patterns; determining a localized zoom ratio based on the local pixel variation patterns; controlling edge sharpness by changing the localized zoom ratio setting interpolation points with spacing between the interpolation points varying based on the localized zoom ratio and a basic zoom ratio; and generating output pixels from the input pixel by interpolation at the interpolating points.Type: ApplicationFiled: December 17, 2004Publication date: July 21, 2005Applicant: Mitsubishi Denki Kabushika KaishaInventors: Jun Someya, Masaki Yamakawa, Yoshiaki Okuno, Hideki Yoshii
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Patent number: 6372593Abstract: First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.Type: GrantFiled: July 19, 2000Date of Patent: April 16, 2002Assignee: Mitsubishi Denki Kabushika KaishaInventors: Nobuyoshi Hattori, Satoshi Yamakawa, Junji Nakanishi
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Patent number: 5954343Abstract: A seal ring to be disposed between two surfaces to sealingly isolate a clearance therebetween into radially inner and outer portions, the seal ring (45) comprisinig a first ridge portion (51) extending through the entire circumference on the first side (46) for sealingly contacting the first surface at a first radial position, and a second ridge portion (52) extending through the entire circumference on the second side for sealingly contacting the second surface at a second radial position different from the first radial position. The seal ring may a generally wave-shaped or S-shaped cross section or include a soft material layer on its surface. The seal ring (65) may also comprise a projection (62) extending from the inner circumference surface of the seal ring in substantially radially inner direction for elastically engaging with a member disposed in the innter circumferential portion of the seal ring.Type: GrantFiled: August 29, 1997Date of Patent: September 21, 1999Assignee: Mitsubishi Denki Kabushika KaishaInventors: Mamoru Sumida, Norihisa Fukutomi
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Patent number: 5826471Abstract: A method for cutting a coil conductor in which a halted conductor wire 2 to be formed into a coil is served by cutting edges 5A, 5B, while simultaneously advancing a cutting edges downstream in the feed direction of the wire. Thus, a pushing back force against the conductor wire and its attendant deformation is prevented when cutting it, whereby the dimensions of the conductor wire are stabilized.Type: GrantFiled: May 12, 1997Date of Patent: October 27, 1998Assignee: Mitsubishi Denki Kabushika KaishaInventor: Mikio Iguchi
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Patent number: 5420610Abstract: A screen display circuit apparatus comprising a plurality of screen display circuits for displaying stored font data as display patterns is provided, whereby the variation of displays is increased, e.g., characters can be shifted or overwritten, etc. when displayed.Type: GrantFiled: March 7, 1994Date of Patent: May 30, 1995Assignee: Mitsubishi Denki Kabushika KaishaInventor: Naoki Takahashi
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Patent number: 5174416Abstract: A linear induction motor for an elevator which includes a secondary, stationary element having a body formed with a plurality of iron-core mounting holes arranged longitudinally of the body at a certain interval, and iron cores disposed in the holes. The stationary, secondary element allows magnetic flux flowing therethrough to pass through the iron cores, thereby reducing the dimension of the total magnetic gap in the motor. Furthermore, the combination of the iron cores in which eddy currents flow with difficulty and the body along which eddy currents tend to flow makes it possible to reduce the ineffective eddy currents.Type: GrantFiled: January 29, 1992Date of Patent: December 29, 1992Assignee: Mitsubishi Denki Kabushika KaishaInventors: Shigekazu Sakabe, Takehiko Kubota, Kazuhiko Sugita, Toshiaki Ishii, Hiroyuki Ikejima
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Patent number: 5096845Abstract: A channel surface with a channel region and a gate electrode opposing to each other is formed approximately vertical to a main surface of a semiconductor substrate in the field effect transistor (FET). A p type (n type) single crystal silicon layer is formed in a hole of an insulating layer on the main surface of the substrate. N type (p type) drain and source regions are formed defining the channel region in the single crystal silicon layer. A gate electrode is formed above the channel region on the side wall of the single crystal silicon layer in the hole. The area of the main surface of the substrate occupied by one FET can be reduced in this manner. A semiconductor device can be provided in which FETs are integrated to a higher degree without degrading performance of the transistors.Type: GrantFiled: March 21, 1990Date of Patent: March 17, 1992Assignee: Mitsubishi Denki Kabushika KaishaInventor: Yasuo Inoue
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Patent number: 5021685Abstract: An input buffer for semiconductor integrated circuits has a resistor (16), capacitor (17) and a logical gate comprising transistors (11, 12, 13) connected in series between a supply line (61) and a ground line (62). The resistor (16) reduces the through current which flows toward the ground (Vss) when the logical gate switches. In a high speed operation, the capacitor (17) supplies current to the logical gate so that any delay which may possibly be caused by the provision of the resistor (16) can be prevented.Type: GrantFiled: April 13, 1990Date of Patent: June 4, 1991Assignee: Mitsubishi Denki Kabushika KaishaInventor: Yuji Kihara