Abstract: An image compression and expansion apparatus is provided which changes an appearance value of quantization table of quantizer/inverse-quantizer without actually changing values of quantization table by carrying out calculation for every processing. An image compression and expansion apparatus which compresses and expands image data comprises a quantizer which linearly quantizes a Discrete Cosine Transform coefficient by different step size for every coefficient location, an inverse-quantizer which inverse-quantizes coefficients obtained in Huffman decoding, and a quantization table which is necessary for quantization and inverse-quantization process comprising: a register for setting a necessary value in response to an outside signal; a data processing unit for carrying out an operation between values set into the register and values in the quantization table to carry out quantization and inverse-quantization operation.

Abstract: A microcomputer is realized having a built-in SIO which is able to correspond to a LAN which requires strict timing control and also correspond to a high speed serial communication. A counter supplies.a clock signal for data shift to an SIO register which performs serial-parallel conversion and vice versa. Two D flip-flop circuits detect the rise of an SRDY signal, an input signal expressing the start of transmission, and give the counter a reset signal.

Abstract: A method of generating electron-beam data used for creating a mask for a layout pattern of a semiconductor integrated circuit by parallel processing a layout pattern of a semiconductor integrated circuit with a parallel data processing unit based on at least one of (i) design layers of the semiconductor integrated circuit, (ii) fabrication processes used in fabricating a mask for the layout pattern, and (iii) segments, each segment being an electron-beam radiation region of the mask. The data processing is divided and divided portions of the data processing are as-signed to respective parallel-connected processing circuits. The parallel data processing unit includes a hierarchy developing A unit for developing, in parallel processing, a hierarchy of the layout pattern for respective design layers by assigning the hierarchy developing to respective parallel-connected processing circuits. The format of data processed by parallel processing is converted into electron-beam data and output.

Abstract: The microcomputer provides with surroundings where data in a RAM can be monitored on the outside without employing an external bus. When a command requesting accessing to a RAM is received from an external monitor, a real time debugger built in the microcomputer confirms that a CPU is not accessing the RAM, and accesses the RAM. On the other hand, when accessing to an emROM, which emulates an actual ROM, is requested from the monitor, the real time debugger accesses one of emROMs which is not being used by the CPU at present.

Abstract: A picture encoding device for compressing picture data using the Huffman encoding system includes a grouping portion for recognizing a group to which an AC coefficient belongs, and a data processing unit receiving a run-length, a group number, and an additional bit, which are output from the grouping portion, for recognizing a ZRL* code and an effective coefficient. If the run-length group number (N/S) is an effective symbol, i.e., not a ZRL* code, the data processing unit transmits the effective symbol to a Huffman encoding portion in the next stage. If the N/S comprises a ZRL* code, a ZRL* code count detection counter is incremented. If an EOB* code follows a ZRL* code, ZRL* codes are deleted in a number corresponding to the count value from the ZRL* code count detection counter. The picture encoding device effectively carries out Huffman encoding without encoding unnecessary ZRL* codes in a Huffman encoding system.

Abstract: A microcomputer includes an analog-to-digital (AD) converter which converts analog data into digital data and then stores a plurality of data bits which represent the digital data, a read signal output unit for producing a read signal for identifying the value of the digital data stored in the AD converter, a gate circuit which, in response to the read signal from the read signal output unit, obtains a plurality of data bits at the uppermost or lowermost end of the digital data from the digital data stored in the AD converter, a skip circuit which, in response to the read signal, obtains remaining data bits, other than the plurality of data bits obtained by the gate unit, from the digital data stored in the AD converter and produces a control signal having a second value which differs according to the value of the remaining data bits and a data identifying unit which identifies the value of the digital data on the basis of the plurality of data bits supplied by the gate unit and by the control signal.

Abstract: An emulator system solving a problem of conventional emulator systems by recognizing a task execution history. In conventional systems, it was necessary for a microcomputer to incorporate a specific task for storing in a memory an identification number and switching time of a task to be executed next in a program to be debugged. The novel emulator system includes a first detector for detecting a write cycle of a microcomputer in which the identification number of a task to be executed next is recorded. A second detector detects the start cycle and end cycle of an interrupt. A measurement memory stores the timing of the write cycle and the timing of the start cycle and end cycle of the interrupt.

Abstract: An electron-beam data generating device generates electron-beam data for creating a mask for a layout pattern of a semiconductor integrated circuit. The device includes processing circuits operating in parallel. The electron-beam data generating device also includes a data processing unit for processing, in parallel, the layout pattern based on at least one of several design layers of the semiconductor integrated circuit, the processes used in fabricating the mask, and segments of the mask, each segment serving as an electron-beam radiation region. The parallel processing is achieved by dividing the data processing and assigning each divided portion of the data processing to respective processing circuits. A format converting unit converts data processed by the processing unit into electron-beam data and outputs the electron-beam data.

Abstract: A voltage-controlled oscillator VCO capable of reliably generating an oscillation even if it, after stopping with electric charges remaining on both of its capacitors, is restarted under the same conditions. Even if the VCO is started with charges remaining on capacitors, N-channel transistors are both turned on because outputs of differential circuits are both at H level. N-channel transistors are both turned off because their gates are connected with the drains of the N-channel transistors. Therefore, in no case, the levels at points C and D as outputs on both sides of latch circuit go to L level at the same time.

Abstract: An output timer includes a capture register for capturing a count value held by a free running up-counter in coorporation with a transmission gate in response to an event signal applied to the output timer. An adder adds a first value stored in another register to the count value captured by the capture register and produces a sum. A comparator compares a count value held by the free running up-counter with the sum and outputs a coincidence signal when the count value and sum are equal to each other. A set-reset flip-flop includes a set terminal for receiving the event signal and a reset terminal connected to the output terminal of the comparator.

Abstract: In a system call issue method and a debug system, during execution of a target program, data transfer is performed between an emulator and an OS kernel forming the target program through a memory field in a RAM. It is checked whether there is a system call issue request in the memory field and if there is the system call issue request in the memory field, the emulator issues a system call.

Abstract: In a program-invocation-count measuring system, first and second identification codes are acquired and exchanged among processes as a broadcast or response signal. The first identification code is used for determining whether there are currently active processes which have been activated by invoking the same program. On the other hand, the second identification code is used for determining whether a response signal received by a process is the same as a broadcast signal transmitted earlier by the process.

Abstract: A microcomputer includes an operation circuit for performing an operation using a reference voltage. A reference voltage input terminal receives the reference voltage from an external device. An output circuit outputs an output signal from the microcomputer to an external destination. The level of the output signal depends on the reference voltage input through the reference voltage input terminal.

Abstract: An image display control apparatus comprising: a plurality of image data storing units, provided corresponding to the plurality of the frames, for storing image data of frames respectively; priority display data storing unit for storing priority display data indicative of displaying image data of each frame on a priority basis; first image data comparing unit for comparing image data output from image data storing means corresponding to a frame having a highest order of the hierarchical relationship among the plurality of the frames with data stored in the priority display data storing unit; and image data selecting unit for selecting and outputting image data output from image data storing unit which stores image data of a frame having priority the priority display data indicates among the plurality of image data storing unit when it is judged that the priority display data are output from the image data storing unit as a result of comparison of the first image data comparing unit.

Abstract: The oscillation-stop detecting device accurately detects the stopping of a clock signal due to various causes. The voltage detecting circuit detects when a clock signal output from the clock signal oscillator remains at a high, a low or an intermediate level, and outputs a clock voltage detection signal. The oscillation-stop detecting circuit outputs a detection signal in response to the voltage detection signal.

Abstract: A fault simulation apparatus includes an MOS transistor output signal strength determining portion for extracting the conductivity type of an MOS transistor in which an event such as a variation in signal level occurs. A control signal value is obtained from a control terminal, and an input signal value is obtained from an input terminal, and output signal strength when the event occurring MOS transistor is turned ON is determined. In the apparatus, fault simulation is performed depending upon the output signal strength determined by the output signal strength determining portion.

Abstract: A jig for dual-side mounting PC boards is composed of a board table which has a board supporting surface, a component receiving hole and a board sucking holes, spacers for placement in the component receiving holes, and a platform having a pressure-reducing space communicating with the board sucking holes. The spacers each have a protrusion for engagement with a spacer positioning hole made in the bottom of the component receiving hole.

Abstract: A phase-locked loop (PLL) circuit includes a low-pass filter, a voltage controlled oscillator that produces a PLL signal having a frequency that differs according to a control voltage supplied by the low-pass filter, a phase detector which receives the PLL signal and a reference signal and detects a phase difference between them to produce an error signal, and a charge pump that, in response to the error signal, supplies a charge to the low-pass filter or extracts a charge from the low-pass filter. The charge pump includes a variable resistance element the resistance of which varies when the error signal is applied, thereby nonlinearly adjusting the charge supplied to or extracted from the low-pass filter with respect to the duration of the error signal from the phase detector.

Abstract: A display control device comprises a work memory including at least a plurality of memory bits each for storing one-bit data indicating whether or not each pixel is inside a figure of plane geometry having a contour such as a polygon, a control unit for scanning each of a plurality of raster scan lines and searching for at least one pixel which can be assumed to form a line segment which partially constructs the contour of the figure so as to generate a control signal for controlling bit inversion to determine the inside of the figure, a selecting unit for receiving the one-bit data of each pixel which is sequentially delivered by the work memory and inverting the one-bit data so as to select one from among the original one-bit data and the inverted one-bit data according to the control signal from the control unit, and output the selected data; a unit for writing the selected data from the selecting unit into a corresponding one of the plural memory bits of the work memory.

Abstract: A microcomputer incorporating two oscillation circuits for generating clocks having different frequencies, which can be driven even when an oscillator is connected only to one of the oscillation circuits, by counting the number of clock pulses of the first or the second oscillation circuit, and selecting the clock of the first or the second oscillation circuit according to the data latched in a latch circuit that is set by an overflow signal outputted when the count value overflows.