Abstract: A notebook-sized personal computer representing consumption-side hardware sends electric power data, which indicates an electric power (including voltage, alternating or direct current, cycle and wave shape) suited to the personal computer, to an electric power supply system through a communication line. In the system, the electric power data of the personal computer is analyzed in an allotter, and the allotter sends electric power data, which indicates an electric power required in the allotter, to an electric power supply adapter through a communication line. The electric power supply adapter converts an electric power received from an electric power company into another electric power matching with the electric power data of the allotter and supplies the converted electric power to the allotter through an electric power line.

Abstract: A random-number generating circuit comprising a plurality of shift registers synchronized with a clock and cascaded together, a circuit that obtains the sum of the outputs of more than one of the shift registers and inputs the obtained sum to the input terminal of the shift register on the first level, and a clock generating circuit that inputs a clock signal to each of the shift registers. One or more of the shift registers have external-signal input terminals and an addition circuit that adds bit data input through the external-signal input terminals to bit data of one or more of the bits stored within. The random-number generating circuit outputs as random-number data the bit data obtained from the addition by the addition circuit.

Abstract: The phase locked loop circuit according to the present invention is configured such that the CPU changes the time constant of the variable LPF filter to an optimum value in accordance with the state of the external signal fed from outside, for example by way of a selection switch activated in accordance with a control signal fed from the CPU, the responsive rate of the PLL circuit is raised, so that it can cope with jittery movements generated due to noise or a fluctuation of the supply voltage of the PLL circuit itself.

Abstract: A debug circuit (2) and a microcomputer incorporating the debug circuit (2). The debug circuit (2) is capable of receiving a trace event from a functional block A as long as a CPU (5) does not generate any trace event, and capable of receiving the trace event from the functional block A in synchronization with a standard clock signal CLK used in the CPU (5) when the reception of the trace event from the functional block A is permitted.

Abstract: Cell assignment section performs an automatic cell assignment according to circuit data 51. Distribution path determining section automatically determines a distribution path between cells. Distribution information extracting section extracts information regarding already determined distribution path. Prescribed-information recognizing section recognizes information on a prescribed portion (end or bend) of the distribution. Additional-distribution-data generating section generates additional distribution data for correcting the width of the prescribed portion. Additional-distribution-data lay-out section lays out the generated additional distribution data for the prescribed portion. This makes it possible to quickly obtain final pattern data in a state of designing a mask that is used for manufacturing a semiconductor integrated circuit device.

Abstract: A ring oscillator clock frequency measuring circuit includes a reference clock count timer and a ring oscillator clock count timer. The reference clock count timer starts its counting of a reference clock signal in response to a start instruction fed from a CPU, and outputs an overflow signal when its counting reaches a preset value. The ring oscillator clock count timer starts its counting of pulses of a ring oscillator clock signal in response to the start instruction fed from the CPU, and continues its counting until the reference clock count timer generates the overflow signal. The frequency of the ring oscillator clock signal is obtained from the count value of the ring oscillator clock count timer. This makes it possible to measure the frequency of the ring oscillator clock signal at high accuracy, and to reduce the current consumption by operating the CPU based on the ring oscillator clock signal after the measurement.

Abstract: When a level of an input signal is suddenly changed to a low level (or a high level), a driving p-channel MOS transistor of a weak driving performance (or a driving n-channel MOS transistor of a weak driving performance) is turned on to control an output-stage n-channel MOS transistor (or an output-stage p-channel MOS transistor) to output an output signal gradually level-changing, and a through-rate correcting n-channel MOS transistor of a middle driving performance (or a through-rate correcting p-channel MOS transistor of a middle driving performance) is turned on to control the output-stage n-channel MOS transistor (or the output-stage p-channel MOS transistor) to output the output signal, of which the level is immediately and sharply changed in its level change beginning period and is successively and smoothly changed in the entire level change period.

Abstract: A cordless power transmission system can transmit and receive power stably without malfunctions. A power transmission terminal transmits default power to an electrical appliance by diffractive electromagnetic waves. The electrical appliance transmits its own unique data and required power intensity data to the power transmission terminal by diffractive electromagnetic waves. A network host assigns an ID to the electrical appliance. Under the control of the network host, the power transmission terminal transmits the assigned ID data and the power with the required intensity to the electrical appliance by rectilinear electromagnetic waves.

Abstract: A character display device includes a memory for storing on-screen display (OSD) character data and wallpaper (background) character data, and shift registers for outputting the corresponding one of those character data stored in the memory in accordance with a command to display one of the OSD character data and of the wallpaper character data. The character display device combines the OSD character data and the wallpaper character data using of a mixer, when the timing for displaying the OSD character data and that for displaying the wallpaper character data coincide with each other, so that both character data can be displayed in a superimposed manner.

Abstract: A phase-locked loop circuit includes a voltage-controlled oscillator that includes a series circuit having a P-channel transistor, N-channel transistor, a third resistor and a first resistor connected in series in this order; a second resistor connected in parallel with a series circuit of the N-channel transistor and the third resistor; and an operational amplifier having its non-inverting input terminal connected to an output terminal of a lowpass filter, its inverting input terminal connected to a connected point of the third resistor and first resistor, and its output terminal connected to a gate of the N-channel transistor. The variable region of the resistance of the parallel circuit consisting of the N-channel transistor and the third and first resistors can be limited, which in turn enables the variable region of the control voltage of the voltage-controlled oscillator including a locking control voltage to be limited to a desired range.

Abstract: By turning OFF a PMOS transistor 15a of a feedback inverter 15 as the signal level at an input node 6 gradually changes from the “L” to “H” level, a high-level output from the feedback inverter 15 to an intermediate node 7 is limited, or by tuning OFF an NMOS transistor 15b of the feedback inverter 15 as the signal level at the input node gradually changes from the “H” to “L” level, a low-level output from the feedback inverter 15 to the intermediate node 7 is limited. Hence, the hysteresis width can be narrowed by limiting the output to the intermediate node 7 from the feedback inverter 15 which functions to expand the hysteresis width.

Abstract: A signal is transmitted to/from an analog circuit portion and a digital circuit portion through an interface circuit portion. Analog circuit portion, digital circuit portion and interface circuit portion are externally supplied with power from different power supplies and provided in different well regions.

Abstract: A watchdog timer includes an instruction decoder, a delay circuit and a counter. The instruction decoder decodes a watchdog timer initialization instruction regularly executed to generate an instruction pulse for initializing the count of the counter. The delay circuit delays the rising edge of the instruction pulse, and supplies the delayed instruction pulse to the counter as a signal for initializing the count. The delay circuit prevents the pulse signal from being supplied to the counter when the operation frequency of the microcomputer is high or when the supply voltage to the microcomputer is low, so that the count of the counter overflows, and the overflow signal causes the microcomputer to be reset. This makes it possible to reset the microcomputer before it runs away, thereby solving a problem of a conventional watchdog timer in that the microcomputer can produce, if it runs away, an unexpected signal from its port before it is reset, and hence can impair the security of the system.

Abstract: An input/output control circuit includes an input/output terminal, a first and second transistors configuring a CMOS circuit, a third transistor for carrying out a pull-up operation, an input control gate, an output control gate, a direction register for determining the direction of input/output direction, a control register for determining the mode of input or output, and a selection circuit connected to the gates for the first, second and third transistors, to the control terminals for the control gates, to the control register and also to the direction register. Since there is no redundant registers in this circuit construction, the whole size of the circuit can be made small, resulting in a reduction of total cost.

Abstract: A microcomputer reset device includes a switching circuit for comparing, after a reset of a CPU is released during power-up, a reference voltage Vref with a second divided voltage Vd2 which is proportional to a supply voltage and is adjusted by the CPU, and for switching, when the second divided voltage Vd2 exceeds the reference voltage Vref, a clock source of the CPU from an internal clock signal to an external clock signal. This makes it possible to solve a problem of a conventional microcomputer reset device in that it is not unlikely that the microcomputer starts its operation before its reset has been completed, which hinders the normal operation of the microcomputer.

Abstract: A demodulator circuit including: a signal generating circuit for generating a sine-wave signal and a cosine-wave signal whose frequencies are same as that of the carrier wave of a modulated signal, a multiplying circuit for multiplying the modulated signal by the sine-wave signal and the cosine-wave signal generated by the signal generating circuit, and a filtering circuit for eliminating the frequency twice as high as that of the carrier wave from each of the results of the computation conducted by the multiplying circuit. Due to this, no restriction is imposed by the frequency of the system clock signal in configuring the system as a whole.

Abstract: A detector of an oscillation stopping, which detects the stopping of the oscillation of external clock 11, without increasing the load of CPU 45 in the micro computer 40, and generates a signal to reset the micro computer or exchanges the system clock from the external clock to an inner clock. In an embodiment, one shot pulse is generated for every standing up and/or down edge of the external clock. A capacitor of the charge-discharge circuit is charged and discharged at every one shot pulse. The voltage of the charge-discharge circuit is watched by a Schmitt circuit. When the voltage of the charge-discharge circuit exceeds a predetermined voltage, a signal for resetting the micro computer is generated. In another embodiment, an inner clock oscillation circuit, comprised of a ring oscillator, for example, is actuated, when the voltage of the charge/discharge circuit exceeds a predetermined voltage, and the system clock of the micro computer is exchanged to the inner clock from the external clock.

Abstract: A circuit simulating apparatus includes a netlist extracting unit extracting a netlist from circuit diagram data, an unnecessary circuit disconnecting unit forming a netlist with an unnecessary circuit disconnected, from the netlist extracted by the netlist extracting unit, based on an unnecessary circuit disconnecting terminal designated by an unnecessary circuit disconnecting terminal designating unit, and a circuit simulation unit performing a circuit simulation using a simulation input file formed by using the netlist with the unnecessary circuit disconnected. As the circuit simulation is performed using the simulation input file formed from the netlist with the unnecessary circuit disconnected, the time necessary for the circuit simulation can be reduced.

Abstract: An automatic input threshold selector includes a maximum value level decision circuit, and an input threshold setting circuit. The maximum value level decision circuit decides, among m+1 level layers defined by m maximum value decision levels, a level layer to which the maximum value of an input signal belongs. The input threshold setting circuit sets an input threshold by selecting one of n input threshold candidates in response to the level layer to which the input signal maximum value belongs. These circuits are implemented as a simple combination of a voltage comparator, logic gates and the like. This makes it possible to solve a problem of a conventional automatic input threshold selector in that its circuit scale and power consumption is rather large because it includes a peak-hold circuit and a bottom-hold circuit.

Abstract: An address match determining device has an address filter memory (22) for storing a matrix or table having a plurality of elements each of which is a 1-bit address match determination data indicating whether or not a corresponding N-bit address code is available, and is distinguished by a pair of a first index composed of the m most significant or high-order m bits of the corresponding address code and a second index composed of the remaining lowest or low-order (N−m) bits of the corresponding address code. A received-address latch (21) extracts the high-order m bits and remaining low-order (N−m) bits from an address code latched thereinto.