Abstract: A memory cache apparatus compatible with a wide variety of bus transfer types including non-burst and burst transfers. In burst mode, a "demand word first" wrapped around quad fetch order is supported. The cache memory system decouples the main memory subsystem from the host data bus so as to accommodate parallel cache-hit and system memory transfer operations for increased system speed and to hide system memory write-back cycles from the microprocessor. Differences in the speed of the local and system buses are accommodated, and an easy migration path from non-burst mode microprocessor based systems to burst mode microprocessor based systems is provided. Various memory organizations are accommodated including direct-mapped or one-way set associative, two-way set associative, and four-way set associative.

Abstract: A memory cache apparatus compatible with a wide variety of bus transfer types including non-burst and burst transfers. The memory cache apparatus includes a random access memory, a host port, and a system port. The memory cache apparatus further includes an input register connected to the host port for selectively writing data to the random access memory and an output register connected to the system port for receiving data from the random access memory and selectively furnishing the data to the host port or the system port. In one embodiment, the input register is a memory write register, and the output register includes a read hold register and a write back register. A cache memory system decouples a main memory subsystem from a host data bus so as to accommodate parallel cache-hit and system memory transfer operations for increased system speed and to hide system memory write-back cycles from a microprocessor.

Abstract: A comparator circuit is provided that determines whether a given value is within a selected compare range. The comparator circuit electronically implements a Ling Adder algorithm to perform comparisons. The circuit operates at a high speed and requires fewer components compared to circuitry implementing a conventional carry look ahead algorithm. The circuit may be implemented in CMOS technology.

Abstract: An output buffer circuit is disclosed that has optimized ground bounce characteristics while maintaining low propagation delay. The output buffer may be incorporated within an integrated circuit and may be embodied in either inverting or non-inverting and in either enabling and non-enabling configurations. The output buffer circuit includes a feedback means coupled to the output terminal of the output buffer and to a pull-down transistor. The feedback means provides a feedback voltage to the gate of the pull-down transistor to regulate the derivative of source current with respect to time. The feedback means includes a pair of field effect transistors and either an inverter gate or a NOR gate coupled across one of the feedback field effect transistors.

Abstract: A resistor located above the semiconductive substrate of an integrated circuit chip can be made smaller than prior art resistors because no area is allocated for resistor contacts. During manufacture, a resistive strip having the width of the intended resistor is formed. A photoresist mask protects the top and sides of the resistive strip where the resistor is located, and etching exposes the ends but not the top and sides of the resistor. Contact to the resistor occurs at the upwardly extending (usually near vertical) end surfaces of the resistor.