Abstract: In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and includes an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features. The trench-typed MOSFET and the trench-typed termination structure may be formed on a DMOS device including an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure may penetrate through the P epitaxial layer into the N epitaxial layer.

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract: A chemical mechanical polishing (CMP) method is disclosed in which a new polishing pad is broken-in and conditioned into a steady operating state while using a silica (SiO2) based CMP slurry and where the broken-in and conditioned pad is afterwards used for polishing patterned workpieces (e.g., semiconductor wafers) with a ceria (CeO2) based CMP slurry. The approach shortens break-in time and appears to eliminate a first wafer effect usually seen following break-in with ceria-based CMP slurries.

Abstract: The present invention relates to a method of assembling a scrubber which includes a motor, a shaft rotatably coupled to and extending through the motor, a shaft pin detachably connected to the shaft, and a disk coupled to the shaft and having a notch located relative to the shaft pin at a predetermined angle with respect to a longitudinal axis of the shaft when properly assembled. In one embodiment, the method comprises providing a tool body configured to partially receive the scrubber, the tool body including a first recess and a protrusion; and placing the tool body adjacent the scrubber to at least partially receive the shaft pin into the first recess of the tool body and to at least partially insert the protrusion of the tool body into the notch of the disk. The first recess and the protrusion are arranged at the predetermined angle to position the notch of the disk and the shaft pin of the scrubber for proper assembly at the predetermined angle with respect to the longitudinal axis of the shaft.

Abstract: Nonvolatile memory cells (110) are connected to a bitline (BL 170). The bitline is also connected to a source/drain region (620) of a transistor (610), a Y multiplexer transistor for example. This source/drain region is exposed to a higher voltage, and hence is made to have a higher junction breakdown voltage, than the other source/drain region (630) of the same transistor. A nonvolatile memory has a plurality of memory arrays (106), a global decoder (438) and secondary decoders (440). The selection signals provided by the global decoder to the secondary decoders for selecting the control gate lines (140) and the source lines (152) are carried by lines (450) running in the row direction. These signals are low voltage signals (between 0V and Vcc). The super high voltages are carried by lines (460) extending in the column direction to reduce noise injection into the control gate lines, source lines, and wordlines (150), and to reduce the parasitic capacitance associated with the super high voltage lines.

Abstract: The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench.

Abstract: A chemical mechanical polishing (CMP) method is disclosed in which a torque-based end-point algorithm is used to determine when polishing should be stopped. The end-point algorithm is applicable to situations where a ceria (CeO2) based CMP slurry is used for further polishing, pre-patterned and pre-polished workpieces (e.g., semiconductor wafers) which have a high friction over-layer (e.g., HDP-oxide) and a comparatively, lower friction and underlying layer of sacrificial pads (e.g., silicon nitride pads). A mass production wise, reliable and consistent signature point in the friction versus time waveform of a torque-representing signal is found and used to trigger an empirically specified duration of overpolish. A database may be used to define the overpolish time as a function of one or more relevant parameters.

Abstract: The present invention relates to a monitoring method for a furnace apparatus. The monitoring method includes powering on the furnace apparatus to a specific power value; recording the rate of increase of the temperature of the furnace apparatus; and comparing the rate of increase of the temperature with a predetermined threshold value, wherein the furnace apparatus is to be replaced when the rate of increase of the temperature of the furnace apparatus is less than the predetermined threshold value.

Abstract: A method for forming a field oxide is disclosed. In one embodiment, the method comprises providing a semiconductor structure having a substrate, a pad oxide, and a patterned barrier layer, performing a dry oxidation process to form a first field oxide on the substrate in a region not covered with the barrier layer by introducing pure dry oxygen, and performing a wet oxidation process to form a second field oxide adjacent the first field oxide by introducing hydrogen and oxygen. The method of the present invention can improve the quality and electrical property of the semiconductor device, increase the yield, and reduce the cost.

Abstract: Embodiments of the invention are directed to a method of forming a bottom oxide in a trench structure. In one embodiment, the method includes steps of providing a semiconductor substrate and forming a trench structure in the semiconductor substrate; performing an PECVD process with TEOS as a source to deposit an oxide layer on the bottom and sidewall of the trench structure and the semiconductor substrate; and removing the oxide layer on the sidewall of the trench structure substantially completely and the oxide layer on the bottom of the trench structure partially to define the remained oxide layer as the bottom oxide layer.

Abstract: The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only has overcome the problem of the electric leakage, but also has the advantages of withstanding a higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of the power device.

Abstract: Embodiments of the invention are directed to an exposure method for preventing wafer breakage, particularly of a trench-type power MOS device. In one embodiment, the exposure method includes: (a) providing a substrate; (b) forming a trench area and a non-trench area on the substrate; (c) carrying the substrate on a hot plate, the hot plate having a plurality of supporters corresponding to the non-trench area; and (d) performing photoresist coating and baking procedures to the substrate. The exposure method of the present invention can prevent wafer breakage due to rapid temperature variation so as to increase the yield and the efficiency of the manufacturing process and reduce the cost.

Abstract: A fabrication method for forming a gate structure through an amorphous silicon layer includes providing a substrate layer, forming an amorphous silicon layer of a selected thickness on the substrate layer at a reaction temperature between about 520° C. and 560° C., and forming a doped amorphous silicon layer in a upper portion of the amorphous silicon layer at a reaction temperature between about 520° C. and 560° C.

Abstract: Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing the polysilicon layer to form a poly oxide layer on the polysilicon layer; (d) forming and defining a photoresist layer on the poly oxide layer for exposing parts of the poly oxide layer; (e) etching the poly oxide layer, the polysilicon layer and the gate oxide layer via the photoresist layer for forming a poly oxide structure, a polysilicon structure and a gate oxide structure; and (f) removing the photoresist layer. The present invention introduces a poly oxide layer instead of the CVD oxide for preventing the photoresist lifting issue.

Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.

Abstract: Embodiments of the present invention are directed to providing a leakage detecting method for use in an oxidizing system of forming an oxide layer so as to shorten leakage detecting time period. In one embodiment, a leakage detecting method for use in an oxidizing system of forming an oxide layer comprises performing oxidizing processes on a plurality of test wafers in a plurality of test runs under a specified operating condition in an oxidizing system having an oxidizing chamber to form oxide layers on the test wafers having a plurality of oxide thicknesses for the plurality of test runs by flowing an oxidizing gas through the oxidizing chamber containing the test wafers. An oxygen concentration of the oxidizing gas exiting the oxidizing chamber is measured in each of the plurality of test runs.

Abstract: A chemical mechanical polishing method is disclosed in which a batch of wafers is first supplied to a low-selectivity, first CMP tool for partly polishing the batch with one or more relatively non-selective CMP slurries (e.g., silica (SiO2) based); and in which the batch of partly-polished wafers is subsequently transferred to a higher-selectivity, second CMP tool which uses one or more comparatively more-selective CMP slurries (e.g., ceria (CeO2) based) to further the polishing of the batch of partly-polished wafers and/or to complete the polishing of the partly-polished wafers.

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench.

Abstract: A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxide layer, the first silicon nitride layer, the first pad oxide layer, and the substrate to form at least one trench; and removing portions of the first oxide layer, the first silicon nitride layer, and the first pad oxide layer in the trench above an upper corner of the substrate in the trench. The substrate includes a lower corner at a bottom of the trench.

Abstract: Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial layer is then selectively etched to form a plurality of DMOS trenches therein. Thereafter, a gate oxide layer is formed over exposed surfaces in the body region and a termination oxide layer is formed to encircle the body region. Afterward, a polysilicon layer is deposited over all the exposed surfaces, and then selectively etched to form a plurality of poly gates in the DMOS trenches and a polysilicon plate having an extending portion toward the body region over the termination oxide layer. By using the termination polysilicon layer as an implantation mask, sources are formed in the body region.