Abstract: A method and a system for optoelectronic matching are disclosed. The method comprises the steps of: S1, enabling an electrical port of a first optoelectronic device to auto-negotiate with a first electrical port to obtain the highest supported speed of the first electrical port, and enabling an electrical port of a second optoelectronic device to auto-negotiate with a second electrical port to obtain the highest supported speed of the second electrical port; S2, encapsulating, by an optical port of an optoelectronic device, a current speed and the negotiated highest supported speed of an opposite end in a transmission protocol, and sending the same to an optical port of another optoelectronic device; S3, obtaining a target speed based on the highest supported speed of the first electrical port and the highest supported speed of the second electrical port; S4, determining whether the current speed is equal to the target speed, respectively.

Abstract: The invention discloses a high-efficiency transmission Ethernet device comprising, a data transmitting module, wherein when receiving a data packet sent by an upper-layer device, and judging that other Ethernet devices in the same local area network for data transmission support a small packet aggregation function, the data transmitting module is configured to aggregately encapsulate all small packets contained in the data packet to form at least one aggregated Ethernet frame and to send it to other corresponding Ethernet devices; and a data receiving module, wherein when receiving data frames sent by other Ethernet devices in the same local area network supporting the small packet aggregation function, performing data parsing on the data frames when judging that the received data frames are routine Ethernet frames, and performing data parsing on the data frames when judging the data frames are aggregated Ethernet frames.

Abstract: The invention discloses a high-efficiency transmission Ethernet device comprising, a data transmitting module, wherein when receiving a data packet sent by an upper-layer device, and judging that other Ethernet devices in the same local area network for data transmission support a small packet aggregation function, the data transmitting module is configured to aggregately encapsulate all small packets contained in the data packet to form at least one aggregated Ethernet frame and to send it to other corresponding Ethernet devices; and a data receiving module, wherein when receiving data frames sent by other Ethernet devices in the same local area network supporting the small packet aggregation function, performing data parsing on the data frames when judging that the received data frames are routine Ethernet frames, and performing data parsing on the data frames when judging the data frames are aggregated Ethernet frames.

Abstract: An on-chip resistor correction circuit includes a first MOS transistor connected between VDD and a reference resistor, the other end of the reference resistor being grounded; an operational amplifier for outputting a first control signal based on a reference voltage and a voltage of the reference resistor; a second MOS transistor connected between VDD and a reference node; a branch where each of the on-chip resistors is located is controllably connected between the reference node and ground; a comparator for generating a comparison signal based on the voltage of the reference node and the reference voltage; and a controller for generating a control signal under the action of the comparison signal to control the branch where each of the on-chip resistors is located to turn on or off.

Abstract: An on-chip resistor correction circuit includes a first MOS transistor connected between VDD and a reference resistor, the other end of the reference resistor being grounded; an operational amplifier for outputting a first control signal based on a reference voltage and a voltage of the reference resistor; a second MOS transistor connected between VDD and a reference node; a branch where each of the on-chip resistors is located is controllably connected between the reference node and ground; a comparator for generating a comparison signal based on the voltage of the reference node and the reference voltage; and a controller for generating a control signal under the action of the comparison signal to control the branch where each of the on-chip resistors is located to turn on or off.

Abstract: A delay line structure and a delay jitter correction method thereof are provided. The delay line structure comprises N delay units and N selectors. An output end of the N?1th delay unit is connected to a first input end of the N?1th selector and an input end of the Nth delay unit respectively, the N?1th selector inputs the N?1th selection signal, an output end of the Nth delay unit is connected to a first input end of the Nth selector, an output end of the Nth selector is connected to a second input end of the N?1th selector, and the Nth selector inputs the Nth selection signal. The time delay units and the selectors are stacked forwards according to the above-mentioned rule until the input ends of the first time delay units are connected with input signals and the output ends of the first selectors are connected with output signals.