Abstract: A Read-Modify-Write operation in a RAID system is done by separating the writing of new data and the writing of new parity, so that they are not done in parallel. This allows recovery to be performed at all stages, without requiring the excessive use of non-volatile cache, and minimizing the amount of time a span has to be locked. The invention accomplishes this by allowing one of the recoveries to be a recovery to the old data, before the write, with a signal to the host that the write operation failed in such a recovery situation, requiring the host to resend the data. This speeds up the entire operation while minimizing the use of resources while only requiring that in the rare instances of a failure during a particular part of the Read-Modify-Write, the host needs to resend the data.

Abstract: The present invention is directed to a novel apparatus for “on-the-fly” data correction and regeneration of a plurality of data read from and stored to a plurality of storage devices. A control circuit is provided for control of data flow to and from the storage devices. The control circuit establishes and maintains a relatively simple semaphore between itself and an interface circuit controlling a FIFO buffer. A mask register is provided as a type of programmable logic AND gate to assert a master ready signal when each of a selected plurality of the interface circuits, one interface circuit per FIFO buffer, indicates that its respective FIFO buffer is ready, either to output or input an entire block. When each is ready, routing and correction commences under control of the control circuit until an entire block has been processed. Each interface circuit includes an associated flip/flop having an output which provides an indication of the ready status.

Abstract: A method and apparatus for reducing the bring-up time upon a transfer of control. This is accomplished by performing the physical level access bring-up prior to fail-over or other transfer, on the devices which are only secondarily controlled by the controller. The media level access is performed only by the controller with primary control of the devices. Upon a failure or transfer by the first controller, a media level access can be immediately performed by the second controller without doing a physical level access first, since this had been done prior to the fail-over or transfer.

Abstract: The present invention is directed to a novel apparatus for “on-the-fly” data correction and regeneration of a plurality of data read from and stored to a plurality of storage devices. A control circuit is provided for control of data flow to and from the storage devices. The control circuit establishes and maintains a relatively simple semaphore between itself and an interface circuit controlling a FIFO buffer. A mask register is provided as a type of programmable logic AND gate to assert a master ready signal when each of a selected plurality of the interface circuits, one interface circuit per FIFO buffer, indicates that its respective FIFO buffer is ready, either to output or input an entire block. When each is ready, routing and correction commences under control of the control circuit until an entire block has been processed. Each interface circuit includes an associated flip/flop having an output which provides an indication of the ready status.

Abstract: A method and apparatus for determining proper cabling and identical device locations between two controllers in a RAID system. Each controller first obtains the port names to which it is attached. The list is then reviewed to determine that there are no duplicate entries. Once this step is completed, the controllers exchange their port name lists. The lists are compared to make sure they exactly match. Finally, the controllers exchange a map of the devices themselves present on two channels. The exchange device maps are compared and must be equal. The two device maps being equal indicate that each storage device is logged on to the network through both I/O ports and is available to each controller.

Abstract: A method for converting between logical and physical memory space which adapts to different RAID types and configurations in a modular form. In particular, a module containing a standard set of conversion algorithms is used for all conversions. The standard set of conversion or translation algorithms operate on a pseudo representation of a RAID array that has all redundant components removed. For each RAID type and configuration, the standard algorithms can be used unchanged if a method is provided to convert the real RAID array representation into the pseudo version and back again. This simplifies both the programming and the debugging. This also makes the software more modular and more easily upgradeable.

Abstract: A memory system including a main memory such as a cache memory and a shadow or back-up cache memory in conjunction with a write cache is disclosed. The shadow memory is coupled to the same data bus as the main memory and is written to simultaneously. Thus, there is no latency between writing to the main memory and writing to the shadow memory. Redundancy is provided for by having a switching circuit which allows control of the shadow memory to be transferred to a second controller upon failure of a first controller. A unique layout arrangement for a RAID (redundant array of independent disks) chassis is also described in which back-to-back circuit boards are mounted in the center of the chassis and a main bus on one board becomes the shadow bus on the other board, providing a mirror arrangement for the circuit boards.

Abstract: A clock failure detection circuit which monitors a clock by comparing the clock to at least one delayed version of itself is provided. The original clock and the delayed version will be offset, such that an edge of one of them can clock a logic circuit to determine if the clock is at the proper level. By setting up the delay so that a clock edge is generated when the clock signal should be low, for instance, a bad output signal will be provided whenever the clock is high instead. This could be caused by the clock being stuck high, or by an irregular pulse width.

Abstract: The present invention is directed to memory subsystems that use redundant arrays of inexpensive disks (RAID). The subsystem enables dual concurrent accesses to the subsystem buffer by the host and RAID engine, which calculates parity information associated with data being transferred between the host and disk drives, by including a dual-ported staging memory where the host and disk drives are coupled to one port and the RAID engine to the other port. Positioning the RAID engine on the opposite side of the staging memory in relation to the host and disk drives allows for pipelined asynchronous memory subsystem operation, improving system throughput.

Abstract: A disk drive in a computer system is equipped with a power storage unit that supplies power to the drive controller when there is a system power interruption, such as a powerdown or a power failure. Once the controller is notified that system power has been interrupted, it will immediately initiate a seek to a reserved location in the disk drive and store the contents of the cache memory at the reserved location. After power has been restored to the system, the controller can load the contents of the reserved cylinders back to the cache memory and complete the pending write operations by writing all of the data items in the cache to their respective final locations in the drive.

Abstract: A method for arbitrating for control of a network medium for transmission, combining aspects of the time slots and collision-based arbitration schemes by dynamically modifying the scheme used in accordance with network load. In a preferred embodiment, this is done by assigning time slots to the various nodes and arbitrating using the time slots when the network is free. If there are no requests for use of the network after a predefined number of time slots, any node can immediately access the network using a collision-detection method without being required to wait for a time slot arbitration procedure.

Abstract: An improvement on the use of parity and a write cache for a RAID by adding a check code for the parity data itself. In addition, the time during which the parity check code is unprotected is reduced by using a single loop to calculate the old parity check code and verify it, determine the new parity information itself from the new write data, and calculate the new parity check code. Rather than cycle through all the parity blocks to calculate the old check code, and verify that it matches what is stored, the old check code is reconstructed block-by-block as the new parity is generated for each block in a loop. In addition, the new parity check code is constructed bit-by-bit at the same time.

Abstract: A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit from seeking access if total transmission activity on the communication medium exceeds a total use threshold value and transmission activity of the node exceeds a local use threshold value, and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.

Abstract: A method and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. More particularly, there is provided a method and apparatus for determining, on restoration of power to a device set, whether or not a write operation was interrupted when power was removed, and for reconstructing any data that may be inconsistent because of the removal of power.

Abstract: Methods and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. A method and apparatus is provided for detecting and reconstructing incorrectly routed data. A method and apparatus is also provided for detecting when one or more physical devices fails to write a block of data, and for reconstructing lost data.

Abstract: An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.

Abstract: The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus by a plurality of SCSI devices coupled to the bus by providing a pseudo busy signal to SCSI devices from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices and control the order in which the devices will be serviced when ready. A plurality of pseudo busy circuits are provided, with one coupled to each device on the bus. Each pseudo busy circuit is controlled by a control signal from the initiator.

Abstract: A network-type data processing system is provided. The system can support multiple simultaneous exchanges of data, and includes multi-port storage devices in which all ports can be active at all times. On initialization of the system, each storage device can announce itself through all of its ports simultaneously.

Abstract: A data storage system having a local processor and a plurality of memory storage elements is used for storing data from one or more external CPUs. The storage system includes a plurality of memory buffers, each coupled to a separate memory storage element. A data path control circuit is programmed by the local processor to control the transfer of data between the external CPUs and the memory buffers. Two interface circuits are coupled between the external CPUs and the memory buffers to provide two data paths for transferring data between the external CPUs and the memory buffers. The data path control circuit contains two independent sequencing circuits for selecting memory buffers. This allows one data path to be used for reading or writing to a number of the memory buffers while the other data path is simultaneously used for a different operation for the rest of the memory buffers.

Abstract: A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit from seeking access if total transmission activity on the communication medium exceeds a total use threshold value and transmission activity of the node exceeds a local use threshold value, and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.