Abstract: An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

Abstract: One example provides an integrated circuit comprising a transistor including a semiconductor channel. The semiconductor channel includes three or more sub-channels, one or more nodes, each node being a junction of at least three sub-channels, and channel ends. A Schottky contact at each channel end forms a source or drain contact, and a gate contact disposed at each Schottky contact controls a barrier conductivity of the corresponding Schottky contact.

Abstract: An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.

Abstract: One example provides a memory cell including a node, and a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first and second electrodes and having at least two polarization states. A first transistor includes a source, a drain, and a gate terminal, with the gate terminal connected to the node. A selector element includes at least a first terminal and a second terminal, with the second terminal connected to the node.

Abstract: The energy density of capacitors can be increased by using a material with differential negative capacitance (NC), which was recently observed in FE materials. Described is a more general pathway towards improved electrostatic energy storage densities by engineering the capacitance non-linearity of electrostatic devices. The disadvantages of regular polarizable materials are overcome by using the NC effect, which ideally has no hysteresis losses, leading to a theoretical efficiency of 100%. By storing the energy mostly in an amorphous DE layer, the break-down field strength is much higher compared to pure FE or AFE storage capacitors. In addition, leakage current losses can be reduced by improving the morphology of the insulating materials used.

Abstract: One example provides an integrated circuit comprising a transistor including a semiconductor channel. The semiconductor channel includes three or more sub-channels, one or more nodes, each node being a junction of at least three sub-channels, and channel ends. A Schottky contact at each channel end forms a source or drain contact, and a gate contact disposed at each Schottky contact controls a barrier conductivity of the corresponding Schottky contact.

Abstract: An integrated circuit element includes a gate, a source, and a drain. In response to a selected drain voltage, a drain-current-to-gate-voltage transfer characteristic of the integrated circuit element to transition from an asymmetric, non-linear first transfer characteristic to a non-linear parabolic-shaped second transfer characteristic with an inflection point having a corresponding inflection point gate voltage value, where drain current values of the second transfer characteristic increase in magnitude as gate voltage values both increase and decrease from the inflection point gate voltage value such that the second transfer characteristic is a rectifying transfer characteristic.

Abstract: An artificial neuron integrated circuit including a polarizable circuit element having a first electrode, a second electrode, and a polarizable material layer disposed between the first and second electrodes, the polarizable material layer changeable between a first polarization state and a second polarization state, in response to receiving a number of voltage pulses across the first and second electrodes, the polarizable material layer to change from one of the first and second polarization states to the other of the first and second polarization states, where each of the number of voltage pulses individually is insufficient to change the polarization state.

Abstract: An integrated circuit comprises a ferroelectric memory cell comprising a ferroelectric film comprising a binary oxide ferroelectric with the formula XO2 where X represents a transition metal. The ferroelectric film is a polycrystalline film having a plurality of crystal grains, wherein the crystal grains are oriented along a predetermined crystal axis, or the ferroelectric film is a monocrystalline film, wherein the ferroelectric film comprises additives promoting formation of the crystal structure of the monocrystalline film and/or wherein the memory cell comprises a crystallinity-promoting layer that is directly in contact with the ferroelectric film and promotes formation of the crystal structure of the monocrystalline film.

Abstract: One example provides a memory cell including a node, and a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first and second electrodes and having at least two polarization states. A first transistor includes a source, a drain, and a gate terminal, with the gate terminal connected to the node. A selector element includes at least a first terminal and a second terminal, with the second terminal connected to the node.

Abstract: An integrated circuit comprises a ferroelectric memory cell including an oxide storage layer, an electrode layer, and an interface layer. The oxide storage layer comprises a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric material comprises, as main components, oxygen and any of the group consisting of Hf, Zr and (Hf,Zr). The interface layer is disposed between the oxide storage layer and the electrode layer and includes at least one element with a higher valence value than Hf or Zr.

Abstract: An artificial neuron integrated circuit including a polarizable circuit element having a first electrode, a second electrode, and a polarizable material layer disposed between the first and second electrodes, the polarizable material layer changeable between a first polarization state and a second polarization state, in response to receiving a number of voltage pulses across the first and second electrodes, the polarizable material layer to change from one of the first and second polarization states to the other of the first and second polarization states, where each of the number of voltage pulses individually is insufficient to change the polarization state.

Abstract: A polarization-based logic gate includes a transistor having a drain and a polarizable material layer having at least two polarization states, the polarization state representing a first logic value, and a resistive element having a first terminal coupled to the drain and a second terminal. A plurality of input/output terminals connected to the transistor and second terminal of the resistive element so as to apply voltages to selected input/output terminals, including a sensing voltage representing a second logic value, with a resulting drain current of the transistor at least partially flowing through the resistive element and representing a result of a logic operation between the first logic value and the second logic value.

Abstract: A reconfigurable field effect transistor (RFET) includes a nanowire, wherein the nanowire comprises two Schottky contacts, as well as two gate contacts partially enclosing the nanowire in cross section. An integrated circuit can be produced therefrom. The aim of producing CMOS circuits with enhanced functionality and a more compact design is achieved in that the nanowire is divided along the cross section thereof into two nanowire parts, wherein each nanowire part comprises a respective Schottky contact and a respective gate contact, and the two nanowire parts are connected electrically to one another via a common substrate and stand vertically on the substrate. In a nanowire-parts-array, between the nanowire parts, a respective top-gate contact and/or back-gate contact can be formed in a substrate defining a substrate plane.

Abstract: A polarization-based logic gate includes a transistor having a drain and a polarizable material layer having at least two polarization states, the polarization state representing a first logic value, and a resistive element having a first terminal coupled to the drain and a second terminal. A plurality of input/output terminals connected to the transistor and second terminal of the resistive element so as to apply voltages to selected input/output terminals, including a sensing voltage representing a second logic value, with a resulting drain current of the transistor at least partially flowing through the resistive element and representing a result of a logic operation between the first logic value and the second logic value.

Abstract: Integrated devices comprising pinched hysteresis loop (PHL) materials in a capacitor or a transistor stack are disclosed. PHL materials include field induced ferroelectrics (FFE), anti-ferroelectric (AFE) and relaxor type ferroelectric (RFE) materials. Each integrated device includes a material stack with a PHL material layer disposed between two electrodes. Application of this material is dependent on inducing of an electric field bias over the stack. According to one option, electrodes having different workfunction values can be employed to induce the required built-in bias field and enable use of PHL materials. According to another option, a PHL material and charges, e.g., a charge interlayer, are disposed between two electrodes such that an induced built-in bias field appears. Integrated devices employing the PHL material stack include memories, transistors, and piezo- and pyroelectric devices.

Abstract: An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.

Abstract: An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.

Abstract: A reconfigurable field effect transistor (RFET) includes a nanowire, wherein the nanowire comprises two Schottky contacts, as well as two gate contacts partially enclosing the nanowire in cross section. An integrated circuit can be produced therefrom. The aim of producing CMOS circuits with enhanced functionality and a more compact design is achieved in that the nanowire is divided along the cross section thereof into two nanowire parts, wherein each nanowire part comprises a respective Schottky contact and a respective gate contact, and the two nanowire parts are connected electrically to one another via a common substrate and stand vertically on the substrate. In a nanowire-parts-array, between the nanowire parts, a respective top-gate contact and/or back-gate contact can be formed in a substrate defining a substrate plane.

Abstract: A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.