Patents Assigned to Naoetsu Electronics Co.
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Patent number: 7700400Abstract: The present invention can finely arrange p+-type diffusion layers and n+-type diffusion layers. A p+-type diffusion layer 2 and an n+-type diffusion layer 3 are simultaneously formed on a back surface 1a of a semiconductor substrate 1 in a state that the p+-type diffusion layer 2 and the n+-type diffusion layer 3 are arranged close to each other, and a back surface 1a side of the semiconductor substrate 1 on which outer end portions of the p+-type diffusion layers 2 and the n+-type diffusion layers 3 are brought into contact with each other is removed thus separating the p+-type diffusion layer 2 and the n+-type diffusion layer 3 from each other and hence, the p+-type diffusion layer 2 and the n+-type diffusion layer 3 can be separately arranged in a state that the p+-type diffusion layer 2 and the n+-type diffusion layer 3 are arranged close to each other.Type: GrantFiled: October 21, 2005Date of Patent: April 20, 2010Assignees: Naoetsu Electronics Co., Ltd., Shin-Etsu Chemical Co., Ltd.Inventors: Tsutomu Onishi, Takeshi Akatsuka, Shunichi Igarashi
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Publication number: 20090020158Abstract: The present invention is a method for manufacturing a solar cell by forming a p-n junction in a semiconductor substrate having a first conductivity type, wherein, at least: a first coating material containing a dopant and an agent for preventing a dopant from scattering, and a second coating material containing a dopant, are coated on the semiconductor substrate having the first conductivity type so that the second coating material may be brought into contact with at least the first coating material; and, a first diffusion layer formed by coating the first coating material, and a second diffusion layer formed by coating the second coating material the second diffusion layer having a conductivity is lower than that of the first diffusion layer are simultaneously formed by a diffusion heat treatment; a solar cell manufactured by the method; and a method for manufacturing a semiconductor device.Type: ApplicationFiled: April 11, 2006Publication date: January 22, 2009Applicants: SHIN-ETSU HANDOTAI CO., LTD., NAOETSU ELECTRONICS CO., LTD., SHIN-ETSU CHEMICAL CO., LTD.Inventors: Hiroyuki Ohtsuka, Masatoshi Takahashi, Naoki Ishikawa, Shigenori Saisu, Toyohiro Ueguri, Satoyuki Ojima, Takenori Watabe, Takeshi Akatsuka, Tsutomu Onishi
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Publication number: 20070264746Abstract: The present invention can finely arrange p+-type diffusion layers and n+-type diffusion layers. A p+-type diffusion layer 2 and an n+-type diffusion layer 3 are simultaneously formed on a back surface 1a of a semiconductor substrate 1 in a state that the p+-type diffusion layer 2 and the n+-type diffusion layer 3 are arranged close to each other, and a back surface la side of the semiconductor substrate 1 on which outer end portions of the p+-type diffusion layers 2 and the n+-type diffusion layers 3 are brought into contact with each other is removed thus separating the p+-type diffusion layer 2 and the n+-type diffusion layer 3 from each other and hence, the p+-type diffusion layer 2 and the n+-type diffusion layer 3 can be separately arranged in a state that the p+-type diffusion layer 2 and the n+-type diffusion layer 3 are arranged close to each other.Type: ApplicationFiled: October 21, 2005Publication date: November 15, 2007Applicants: NAOETSU ELECTRONICS CO., LTD., SHIN-ETSU CHEMICAL CO., LTD.Inventors: Tsutomu Onishi, Takeshi Akatsuka, Shunichi Igarashi
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Patent number: 5240882Abstract: This invention relates to a process and an apparatus for making a substrate of a semiconductor of a monolithic silicon wafer, or the like, for use as a discrete element such as a transistor, diode, or the like. In particular, the invention is directed to re-slicing the silicon wafer into two further pieces, to dope impurity diffused layers on both sides but not to provide any impurity diffused layer in the core portion of the silicon wafer. The re-slicing process is performed from substantially the center portion of its core thickness of the wafer so as to provide each re-sliced surface as a plain surface without any impurity diffused layer and for doping a further new impurity diffused layer, so as to obtain two pieces of a substrate as discrete elements simultaneously from one piece of the wafer by the re-slicing process and apparatus of the invention.Type: GrantFiled: July 28, 1992Date of Patent: August 31, 1993Assignee: Naoetsu Electronics Co.Inventors: Tsutomu Satoh, Kouichi Nishimaki
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Patent number: 4433510Abstract: The present invention relates to an improvement in the lapping method of wafer-like work pieces in a lapping machine to lap the work pieces by sandwiching them between relatively rotatable upper and lower surface plates, in which the thickness of the work pieces under lapping is determined by an in-machine manner with a sensor mounted on the upper surface plate. Different from conventional lapping methods with an in-machine measurement of the thickness, the thickness of the work pieces is computed only once at regular intervals corresponding to one relative revolution of the surface plates so that the errors due to the operation per se of the lapping machine such as the undulated revolution of the surface plates, vibration of the machine and the like can be eliminated and very much improved control means for the thickness of the work pieces under lapping can be obtained.Type: GrantFiled: April 2, 1982Date of Patent: February 28, 1984Assignees: Shin-Etsu Engineering Co., Ltd., Naoetsu Electronics Co., Ltd.Inventors: Kiyoo Katagiri, Mitsuo Honda