Abstract: A battery-powered portable radio device saves on the overall power consumed by the whole device by skipping unnecessary read, write, and refresh cycles of the internal main memory DRAM core. Streaming data input from a radio receiver is analyzed by a vector processor. The DRAM main memory and the vector processor itself share real estate on a common semiconductor chip. This allows a very wide row of DRAM memory to communicate 1024 bits wide with an eight-line cache. Six lines of the cache are reserved for memory operations, and two lines are reversed for I/O operations. Streaming data from the radio receiver is stored up in the DRAM main memory via the two I/O cache lines. As raw data is needed by the vector processor, whole DRAM rows are downloaded to the six lines of memory cache. The single-instruction multiple data vector processor rolls intermediate data around through the cache without causing it to write back to the DRAM.

Abstract: A DRAM memory saves on the overall power consumed by the whole device by skipping unnecessary read, write, and refresh cycles of the internal memory core. Because each such cycle costs power, skipped cycles save power. Specifically, read cycles are not always automatically followed by write-back cycles that restore the read-data, e.g. due to the destructive-read nature of the DRAM. Such write-back cycles are only allowed when they can be postponed no longer, and the data written are actually used sometime later. Data that needs only to be read back once, and that have thereby served their purpose, are not written-back. Simple refresh cycles involving unused rows, or rows that have been destructively read and not yet written-back, are skipped and not refreshed. Data rows that are read from the memory core are held in the peripheral circuits in a way that simulates a cache.