Abstract: A method of manufacturing a semiconductor device including alternately repeating a process of forming a first metal oxide film including a first metal element and a process of forming a second metal oxide film including a second metal element on a substrate accommodated in a processing chamber, so as to form a third metal oxide film including the first and second metal elements with a predetermined composition ratio on the substrate. One of the first and second metal elements of the third metal oxide film has a concentration higher than a concentration of the other, and one of the first and second metal oxide films including the higher-concentration metal element is formed in a chemical vapor deposition (CVD) mode or an atomic layer deposition (ALD) saturation mode, and the other of the first and second metal oxide films is formed in an ALD unsaturation mode.

Abstract: A resist post is formed on a connection pad of a semiconductor chip, and the semiconductor chip and the resist post are covered by a heat resistant insulating layer. A surface of the insulating layer is next polished by CMP or the like, thus an upper surface of the resist post being exposed. The exposed resist post is then removed by developing processing or the like, thus forming a through hole. A conductor is then embedded in the through hole by plating, thus forming a connecting conductor, and wirings are formed. A method of forming the connecting conductor does not impart damage to the semiconductor chip.

Abstract: A built-in self test circuit (BIST circuit) in an LSI includes a verification test pattern generator for generating verification test pattern which is used for verifying the connections in the LSI including the BIST circuit in the design stage thereof, and another test pattern generator which is used to test the function of the LSI.

Abstract: A nonvolatile semiconductor memory device includes diffusion layers formed in a semiconductor substrate, a gate insulating film formed on at least a portion of a channel region between the diffusion layers in the semiconductor substrate, and a control gate formed on the gate insulating film. The nonvolatile semiconductor memory device also includes electric charge storage insulating films formed on side surfaces of the control gate, memory gates formed on side surfaces of the sidewall insulating films to be higher than the sidewall insulating film, and a silicide film formed to connect the memory gates and the control electrode.

Abstract: A drive power supply circuit for driving liquid crystal display of the present invention generates necessary levels in an LCD drive power supply circuit that generates drive levels for LCDs in an LCD controller/driver IC by means of switching connection to capacitors in a constant manner or in synchronism with the timing of LCD driving. It allows reduction in number of the components such as amplifiers for level generation and external capacitors, which in turn reduces current consumption of the entire system, chip areas, and mounting areas.

Abstract: To provide a semiconductor integrated circuit device that reduces charging and discharging currents flowing through clock tree synthesis, thereby reducing current consumption of entire circuits of the semiconductor integrated circuit device. In a semiconductor integrated circuit device including a clock synchronous type circuit that operates in synchronization with either of rising and falling edges flank of a reference clock and a plurality of clock buffer circuits for distributing the reference clock to the clock synchronous type circuit, each clock buffer circuit is constituted from a first transistor that drives a load at one of the edges flank of the reference clock with which the clock synchronous type circuit does not operate in synchronization and a second transistor that drives the load at the other edge flank of the reference clock. A gate width of the first transistor is set so that a change in the edge flank is slowed down, provided that a pulse waveform of the reference clock is not destroyed.

Abstract: It is an object of the present invention to provide a semiconductor memory device with a suitable redundancy circuit and an address conversion circuit, wherein external addresses are allocated to both a memory cell array which needs refresh, typically DRAM and another memory cell array which does not need refresh, typically SRAM.

Abstract: A monolithic semiconductor device is constructed by a plurality of repetitive cells each including one circuit section and one current source for supplying a current to said circuit section, and a plurality of first impedance circuits, each connected between the current sources of two of the repetitive cells, for reducing the effect of cell mismatches among the repetitive cells.

Abstract: Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

Abstract: In a chemical mechanical polishing method for polishing a low-k material insulating layer formed on a semiconductor wafer, aqueous abrasive slurry composed of a water component, an abrasive component, a first additive for making the low-k material insulating layer of the semiconductor wafer hydrophilic in nature, and a second additive for adding acidity to the aqueous abrasive slurry, is prepared. The aqueous abrasive slurry is feed to a rotating polishing pad having a larger diameter than that of the semiconductor wafer. The low-k material insulating layer of the semiconductor wafer is applied and pressed onto the rotating polishing pad while rotating the semiconductor wafer in the same rotational direction as that of the rotating polishing pad, whereby a polishing rate of the low-k material insulating layer of the semiconductor wafer is improved.

Abstract: There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch becomes “H” level, whereby NFETs turn ON. A voltage dividing circuit comprising resistances and current mirror differential amplifiers are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage). As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch becomes “L”, whereby the NFETs turn OFF. As described here, the NFETs is kept OFF in the other time period than when needed, in order to reduce the power consumption.

Abstract: A device has a bit line pair including first and second bit lines, a sense amplifier commonly connected to the bit line pair, and first and second cells connected at intersecting portions of first and second word lines and the first and second bit lines. In a normal mode, the first and second word lines are assigned separate addresses, whereas in a partial mode, the first and second word lines are assigned the same address. The first and second cells complimentarily store one bit of data. In storing a data in a first cell of two cells comprised in a twin cell into a second cell when set to the partial mode, the second word line is activated based on a trigger signal generated by a refresh timer during a precharge period for the bit line pair, and subsequently the precharge is completed.

Abstract: A semiconductor capacitor configured so as to use buried wirings, as electrodes, formed in an interlayer dielectric is provided on a semiconductor substrate which is capable of preventing an increase in a number of manufacturing processes with occurrence of parasitic capacity being suppressed. The semiconductor capacitor has a capacitive insulating film made up of an etching stopper film formed only in a region being sandwiched between a via plug serving as an upper electrode and a lower electrode, in which the capacitive insulating film is not formed in a region other than the facing region.

Abstract: There is provided a solid-state image sensor including a photoelectric transfer section and a CMOS circuit section both formed on a common semiconductor substrate in accordance with a common process, the solid-state image sensor outputting a signal indicative of a variation in potential caused by electric charges generated in the photoelectric transfer section, the solid-state image sensor including (a) a semiconductor substrate having a first electrical conductivity, a first voltage being applied to the semiconductor substrate, (b) a first well layer formed in the semiconductor substrate, the first well layer having a second electrical conductivity and defining a photoelectric transfer section, a second voltage being applied to the first well layer in such a manner that the first well layer is inversely biased relative to the semiconductor substrate, (c) a second well layer formed in the semiconductor substrate, the second well layer having a first electrical conductivity and partially defining a CMOS circui

Abstract: A semiconductor device is fabricated by forming a first insulating layer, in which an etch stopper and a first contact plug are formed so that the etch stopper surrounds an end portion of the first contact plug and the latter extends through the first insulating layer across its opposite surfaces. On the first insulating layer is formed a second insulating layer which is selectively etched to form a throughhole extending downwards to the end portion of the first contact plug. A second contact plug is formed in the throughhole to establish a direct electrical connection with the first contact plug. Due to the presence of the etch stopper, the throughhole can be aligned with an increased margin of tolerances.

Abstract: The coefficient matrix, corresponding to the simultaneous linear equations to be solved, is divided into a plurality of row sets. The row sets as divided are processed in a parallel fashion, and entries specifying the nonzero elements contained in the first to nth row sets are added to the entry sets E1 to En. Moreover, in regard to each row set, fill-ins which take place at the time of eliminating the ith variable are obtained in a parallel fashion, and entries specifying the fill-ins are added to the entry sets E1 to En. The coefficient matrix is compressed using those entry sets E1 to En.

Abstract: In a solid-state imaging device, an insulation film is used to fill a separating region that divides a charge transfer electrode in the row direction, thereby achieving flattening, after which an interlayer insulation film and a metal light-shielding film are formed.

Abstract: There is presented a structure in which outlines of a metal interconnection 111 that is laid in an interlayer insulating film are covered with a barrier metal film 110. As the material for the barrier metal film 110, TaN or the like is utilized.