Abstract: An elevation regulator of display, comprising a base member 1, and an elevation member 3 moving up and down with respect to the base member 1. The elevation member 3 is provided with a part 6 for fixing a display D. The base member 1 is provided with spiral springs 2, 2 being uncoiled as the elevation member 3 lowers to urge the elevation member 3 upward.

Abstract: A liquid crystal display device is provided. An image memory (4) stores therein input pixel data (Rin, Bin, Gin) on a frame-by-frame basis. Differencing circuits (23 to 25) calculate respective difference data ((Rin−Gpre), (Bin−Rin), (Gin−Bin)) on a pixel-by-pixel basis. Comparator circuits (27, 28, 29) output a pulse when the difference data is greater than a difference level (DLV). Counter memories (30 to 32) perform a counting operation each time the pulse is inputted thereto, and output respective counts (FLN_R, FLN_B, FLN_G) after the counting operation for one line. Comparator circuits (34 to 36) output a pulse to skip flag registers (37 to 39), respectively, when the respective counts are greater than a skip level. Skip flags (SPF_Ri, SPF_Bi, SPF_Gi) corresponding to a current line are set at “1.” A gate pulse for the line corresponding to the skip flags “1” is skipped. This reduces the write time of image data.

Abstract: A display device which is suitable for connection to a computer etc. allows an operator to freely set a power saving mode to suppress the wasteful consumption of power. Power reduction means reduces, in a plurality of modes, the power supplied to device components included in the display device. Power management output selecting means sets any of the plurality of modes on the basis of a selection made by an operator. Signal detecting means monitors horizontal and vertical synchronizing signals sent from a computer and detects as a trigger signal a state in which at least one of them is not being received. In response to the trigger signal being detected, power management signal output means gives an instruction to the power reduction means to perform the set mode.

Abstract: A movable part 10 of a display orientation adjustment apparatus H is attached to a rear surface of a display, and pivotably supported by a base 20, and its pivotal motion is restricted by a stopper 50 within a permissible range. If the movable part 10 is pivoted beyond the restricted range by a pivoting force of a predetermined magnitude or greater, the stopper 50 is released. Therefore, even if the display is pivoted inadvertently beyond the permissible range of the pivotal motion, breakage of components thereof would never take place, and its normal state of use can easily be restored.

Abstract: There is provided an image signal repeater apparatus with a simple construction, which can prevent the accumulation of jitter even if the image signal repeater apparatuses are connected in multiple stages, and which enables the reception of image signals of various frequencies.

Abstract: The display re-imaging system comprises a monitor (1) for display re-imaging and a television camera (30) having a display of the monitor for display re-imaging in a part of a field of view of the television camera. The monitor (1) consists of an LCD monitor comprising a back light (11) including cold cathode fluorescent lamps (11-1 to 11-4) as a light source having a prescribed color temperature, and a non-self-light-emitting-display panel (13) for selectively transmitting light emitted from the back light according to an image signal. The, color temperature of the cold cathode fluorescent lamps (11-1 to 11-4) is adjusted to a level corresponding to a reddish color to match with the color temperature of the re-imaging environment.

Abstract: An MPU storage device 114 stores a device address of an image display device 11, and an MPU identification processing device 113 acquires and retains the device address stored in the MPU storage device 114. The MPU identification processing device 113 acquires the device address from a device information storage device 122 or an MPU identification processing device 123 according to a DDC communication protocol, using an output side data sending and receiving device 115. The device information storage device 122 stores EDID, and the NPU identification processing device 113 acquires EDID stored in the device information storage device 112, compares it with the EDID acquired from the image display device 12, extracts common data, and stores it in the device information storage device 112 as common EDID data of the image display device 11 and the image display device 12.

Abstract: An image display in which occurrence of beat noise can be suppressed without adding noise to an image in a pixel converting process is provided. The frequency of a data clock is preset to a value at which beat noise is not apt to occur (a value such that one of the dot clock frequency of the input analog video signal and the frequency of the data clock is not equal to or close to an integral multiple of the other) for each kind of the input analog video signal and is stored as a frequency correspondence list in a memory MM. In accordance with the kind of the input analog video signal, a control block 4 selects the set frequency of the data clock and allows a data clock generating block 6 to generate a data clock Cd. Consequently, at the time of a pixel converting process performed by a signal processing block 5, without adding noise to an image, occurrence of beat noise is suppressed.

Abstract: A difference in sampling data of continuous two pixels in a digital image signal is detected. A CPU monitors the value of an output signal and determines a control value of a control signal so as to make the difference greatest. In a sampling clock generation section, a sampling clock that is synchronous to a dot clock by a synchronous signal and the control signal is generated. When the difference becomes greatest, it is possible to sample an image signal level that is less susceptible to influences from rounding, and consequently to adjust the phase of the sampling clock without an input signal having a specific pattern.

Abstract: The present invention belongs to a technical field for manufacturing a three-dimensional structure for an electronic device such as a radio wave shielding member through extension working of a metal plate having cuts. In conventional three-dimensional working of a metal plate, there is a problem in that a non-extension portion is wrinkled depending on extension of a cut. In the present invention, a connecting portion (3) extended in a second direction (D2) is provided at an equal pitch (p) in a first direction (D1) through an opening (4) having a rectangular cross-section in an intermediate portion (PB) between a cut forming portion (PC) having cuts (2) provided like a zigzag in the first direction (D1) and a non-extension portion (PA) having no cut in a metal plate (1). Consequently, even if the cut forming portion (PC) is extended, the connecting portion (3) is simply squashed and contracted and a boundary line (BL) portion is not deformed.

Abstract: In order to automatically distinguish a type of cable connected to a display apparatus, and transmit appropriate specification information to a host, when a host 10 and a display apparatus 100 are connected via a DVI-D to DVI-D cable 14 for digital signal, a DDC 5V from the host is applied to an emitter of a detection transistor 19, and a lower voltage due to a resistor 17 is applied to its base so that the detection transistor turns on. A collector voltage thus becomes an H level so that a multiplexer 21 is switched to the side of a non-volatile memory 23 in which a digital EDID is stored. When they are connected via a D-Sub to DVI-I conversion cable 15 for analog signal, a DDC 5V terminal and an HPD terminal of the cable are short circuited, so the detection transistor turns off, the collector voltage becomes an L, and the multiplexer is switched to the non-volatile memory side in which an analog EDID is stored.

Abstract: An object is to eliminate the effect of jitter in a sampling clock to realize proper sampling of a video signal. An A/D converter (1) samples a video signal in synchronization with a sampling clock (VCLK) at a rate of a period which is ½ times the video period. The phase of the sampling clock (VCLK) is corrected in a phase correcting circuit (9). The sampled signals are held alternately as data (DL) and (DR) in two latches (14) (15). A data switching portion (16) selects output signals from one of the two latches (14) and (15). A calculating portion (21) calculates an absolute difference value (&Dgr;D) between the data (DL) and (DR) in each video period. A calculating portion (22) calculates a maximum value (Dmax) among the absolute difference values (&Dgr;D) in one frame.

Abstract: An object is to control a picture display device from an image signal generating device (e.g. a PC) by using only a cable for transferring an image signal without using a USB cable or the like, so as to adjust the chromaticity, brightness, contrast, etc., in the picture display device and also to set r table data and OSD data and to switch the screen size etc. In a picture display control system, screen adjusting control information for adjusting the screen is added to an image signal outputted from an image signal generating device (1) and sent to a picture display device through an image signal cable, and the picture display device detects the screen adjusting control information from the image signal and adjusts the screen on the basis of the detected screen adjusting control information.

Abstract: A geomagnetism sensor (2) outputs the vertical magnitude of geomagnetism as a detection signal (Vy). An A-D converter (5) converts the detection signal (Vy) into digital data which in turn is supplied to a CPU (6) together with data from a memory (1). The CPU (6) performs a computation based on a vertical deflection signal (VH), the data from the memory (1) and the detection signal (Vy) to provide parameters (hposi, yvj, vcancel) for determining current values to be supplied to a deflection yoke (13), a convergence correction coil (14) and a beam landing correction coil (15). D-A converters (7-9) convert these parameters into analog signals. Drive circuits (10-12) receives the analog signals provided by conversion to generate current for driving the deflection yoke (13), the convergence correction coil (14) and the beam landing correction coil (15). Image variations under the influence of the vertical component of geomagnetism are automatically corrected.

Abstract: An image signal generating device 14 of an image signal generator 11 is connected to an image display apparatus 12 with a maximum resolution of SXGA (1280×1024), and to an image display apparatus 13 with a maximum resolution of XGA (1024×768). The resolution of the image signal which the image signal generator 11 generates is set so as to be the same as the resolution of the image display apparatus 12 which can display the highest resolution, amongst all of the image display apparatuses 12 and 13 which are connected. Moreover, in the case where the image display apparatus 13 for which the resolution which can be displayed is low is included within the image display system, the image signal generator 11 outputs as the net image signal, an image signal only for the range of the resolution which can be displayed, for the page which is to be displayed on this image display apparatus 13.

Abstract: An object is to reduce the time and trouble at the time of switching pages, by displaying two or more pages at the same time on one image display apparatus. A image signal generator 11 outputs a net of image signal, a synchronization signal corresponding to the net of image signals, and a transmission index signal substituted for one part of the net of image signals, and applies these in parallel to the image display apparatuses 13 and 14. In the case where a plurality of image display apparatus numbers are set for the image display apparatus 13, the image display apparatus numbers together with the locations where the signals for the respective image display apparatus numbers are displayed are set.

Abstract: When performing A/D conversion on image signals, when reducing noise that is caused by jitter by adjusting the phase of the sampling clocks, even if the input waveform has considerable waveform distortion such as a triangular wave, it is possible to reliably reduce this noise. Input analog image signals are converted into digital image data using sampling clocks from a PLL circuit by A/D conversion means. Next, image data that has delayed by a 1 clock delay circuit is subtracted from the digital data by a subtracter. The maximum value of one screen of the subtracted output is then determined, and 5 is subtracted therefrom to provide a threshold value. A comparator compares the subtracted output and the threshold value, and outputs a signal when the subtracted output is greater than the threshold value. A counter then supplies the count value of these signals to a CPU, and the CPU controls the phases of the sampling clocks using a switch.

Abstract: There is provided a multi-sync type of display apparatus that enables changes in input signals to be accurately determined while increasing the accuracy when identifying input synchronization signals. When input synchronization signals Wa are within a predetermined phase difference, a pseudo synchronization signal generation apparatus formed by a frequency detection section 7 and a pseudo synchronization signal generation section 8 generates pseudo synchronization signals Wd that are synchronized with the input synchronization signals Wa. If the input synchronization signals Wa exceed a predetermined phase difference, pseudo synchronization signals Wd that have the frequency of the synchronization signal directly before the input synchronization signals Wa are generated. A phase comparison section 9 compares the pseudo synchronization signals Wd and the input synchronization signals Wa, and outputs comparison result signals when the phase difference exceeds a predetermined phase difference.

Abstract: In an image display apparatus, based upon such a relationship among previously measured power consumption in a power save mode, an application voltage and application time thereof, and also rising time of a screen when the power save mode is released, a heater application voltage and application time of this heater application voltage are calculated in order to realize power consumption and rising time, which are required with respect to each of modes. Based upon the calculation results, either a duty ratio of a switched voltage or application time of this heater application voltage are controlled. At the same time, when the power save mode is released, a higher voltage than the heater application voltage in the normal display mode is applied only for the calculated time period.