Abstract: Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.

Abstract: An improved method of decoding the Partial-Response Signaling type inter-bin distortion in receiver-end windowed DMT system is disclosed. The method exploits the Maximum Likelihood Sequence Estimation, which yields certain improvements over the conventional DFE-type decoding of PRS signals. Simulation results are shown for the case wherein AWGN is substantially the only impairment. Since in this case the noise samples at the neighboring frequency bin outputs bear correlation of the same type as the correlation introduced among data symbol samples, a trellis imbedded noise prediction/cancellation approach has been devised. It has been shown that performance degradation can be reduced from almost 8 dB to just 1 dB, compared to performance figures with no windowing. Possible applications of this method are for xDSL and wireless OFDM systems.

Abstract: A receiver for improving the performance of conventional Discrete Multitone Modulation (DMT) based Asymmetric Digital Subscriber Line (ADSL) modems, in the presence of noise and/or interference. A demodulator having an FFT followed by a single-tap-per-bin frequency-domain equalizer is augmented by an additional data-path utilizing windowing or pulse shaping. Windowing is done independently for each symbol over the orthogonality interval and efficiently in the time domain or frequency domain. A decision feedback equalizer at the output of the windowed data-path cancels inter-bin-interference created by windowing.

Abstract: A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space are introduced into the code. Statistics are obtained about frequency of occurrence instructions, wherein said statistics include frequency of occurrence of two consecutive instructions. The program is parsed to identify occurrence of instructions or instruction pairs. The identified instructions are replaced with an address to a compressed bus-word table. An address mapping is generated from uncompressed address to compressed addresses.

Abstract: Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.

Abstract: The present invention describes active double-balanced mixers. The mixers use an isolation and matching section that provides RF section input matching and superior isolation between the LO and RF port. The mixers can be implemented using an inexpensive semiconductor processing technology, obviating the need for matching inductors and facilitating a low-cost, low-power fully integrated wireless receiver.

Abstract: One or more logical domains may be utilized for partitioning and reorganizing a single physical domain or a search space constituted by a plurality of physical domains. Logical domains include at least one page selected from the plurality of pages in the physical domain. Responsive to a request for information, each logical domain may be ranked according to subject matter relevance to the information requested. Definition and relevance ranking of logical domains enables Web site mapping which supports multi-granularity and content-sensitivity in response to a request for information. A multi-granular site map presents users with differing levels of detail, from a general overview of site topology to detailed views of specific areas of the map. A topic-focused site map presents users with a general view of site topology with a detailed view of an area of the site which contains information of interest.

Abstract: Hierarchical hybrid optical networking is based on balancing cost and performance of optical networks by providing transparent (optical) switching of subsets of wavelengths in addition to opaque (electrical) switching of individual light paths. Effective use of wavelength-subset switching requires aggregating and deaggregating wavelength subsets in a simple, cost-effective manner. Non-uniform wavebands are introduced and analyzed their performance advantage as compared with uniform wavebands. Also proposed are several architectural options for a hierarchical hybrid optical cross-connect system that combines non-uniform wavebands and improved utilization of OEO ports.

Abstract: A feed-forward dc-offset canceller, for use in direct conversion receiver (DCR) architecture wireless systems, in which dc-offset is estimated from the down-converted signal at the mixer output, and the offset is cancelled before applying the signal to the analog baseband section. A linear digital filter estimates and tracks the dc-offset, which is subtracted from the down-converted signal before the analog baseband input. The response of the filter can be adjusted by its coefficients according to different environments and standard requirements. Although higher order filters can be used depending on the requirements, preferably, a first order recursive filter is used as it has the advantages of being a very simple and efficient structure.

Abstract: A test system for a circuit board, wherein said circuit board has a plurality of cores such that at least one of said plurality of cores is adapted to use a test protocol independent of a communication fabric used in the circuit board.

Abstract: A document partitioning (flat clustering) method clusters documents with high accuracy and accurately estimates the number of clusters in the document corpus (i.e. provides a model selection capability). To accurately cluster the given document corpus, a richer feature set is employed to represent each document, and the Gaussian Mixture Model (GMM) together with the Expectation-Maximization (EM) algorithm is used to conduct an initial document clustering. From this initial result, a set of discriminative features is identified for each cluster, and the initially obtained document clusters are refined by voting on the cluster label for each document using this discriminative feature set. This self refinement process of discriminative feature identification and cluster label voting is iteratively applied until the convergence of document clusters.

Abstract: A programmable security processor for efficient execution of security protocols, wherein the instruction set of the processor is enhanced to contain at least one instruction that is used to improve the efficiency of a public-key cryptographic algorithm, and at least one instruction that is used to improve the efficiency of a private-key cryptographic algorithm.

Abstract: Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. A code decompression engine having plurality of dictionary tables, coupled with decoding circuitry and appropriate control circuitry, is coupled between the processor core and the instruction cache. The code decompression engine provides one-cycle decompression of compressed instructions that are intermixed with uncompressed instructions, thereby increasing processor-to-memory bandwidth and avoiding processor stalls.

Abstract: This paper provides a new image segmentation algorithm for object-based image retrieval. The system partitions multi-dimensional images into disjoint regions of coherent color and texture. In order to distinguish the object contour lines from texture edge, the description length of the line is used as discriminating criteria. Visual attribute values are assigned to each region.

Abstract: A hardware acceleration system for functional simulation comprising a generic circuit board including logic chips, and memory. The circuit board is capable of plugging onto a computing device. The system is adapted to allow the computing device to direct DMA transfers between the circuit board and a memory associated with the computing device. The circuit board is further capable of being configured with a simulation processor. The simulation processor is capable of being programmed for at least one circuit design.

Abstract: An apparatus for receiving a discrete multi-tone (DMT) signal representative of a series of input symbols and including a plurality of orthogonal sinusoidal subchannels of finite length for each input symbol, the apparatus including a plurality of delay circuits, each operable to receive the DMT signal and produce a delayed DMT signal; a plurality of windowing circuits, each operable to receive a respective one of the delayed DMT signals and produce a windowed DMT signal; at least one finite duration fast Fourier transform (FFT) circuit, operable to receive the windowed DMT signals and produce respective complex signals representing a plurality of bins corresponding to the subchannels of the DMT signal; a plurality of multiplier circuits, each operable to produce a product of (i) a complex factor for compensating for a respective phase shift introduced by a corresponding one of the delay circuits, and (ii) a respective one of the complex signals; an equalizer circuit operable to receive the products from the

Abstract: A novel architecture and implementation of a Round-Robin Scheduler (RRS) for high capacity ATM switches is presented. A port is selected from a set of alternating real-time/non real-time priority ports, based on the priority of the port, the minimum cell-rate (MCR) assigned to the ports and the backpressure signals coming from the output buffers. A fast implementation of the scheduler was derived using a binary tree structure. The nodes in the binary tree act as “cut through” switches, and thus the scheduler is able to operate at high speed. This scheduler is amenable for implementation in high speed silicon technology. It is compact in terms of logic gate requirements, very scalable and is a viable option in Gigabit ATM switches.

Abstract: A method for estimating an association between the media objects and the seed Web page accessed by a user. The method is employed in the context of a Web space on a network having Web pages and links between those Web pages modeled as a directed graph. Each Web page comprises a set of media objects and a page author. For each object a size, a user preference and a page author preference are determined. The network has an available pre-fetch bandwidth. The method calculates a weight for each Web object by applying preference rules defined by and user preference and page author preference to the contents of the set of media objects. Next, a random walk graph is generated, and object gains are calculated by finding a steady state distribution of the random walk graph. The object gain represents an association between the object and the seed Web page.

Abstract: An Apparatus for non-linear per-bin adaptive equalization in orthogonal multi-carrier data transmission systems with the Nyquist sub-channel spectral shaping and T/2 staggering of in-phase and quadrature components is disclosed. A previously introduced linear equalization embodiments are augmented by up to three, or more decision feed-back filters, to improve performance in presence of narrow-band interference (NBI) in wire-line and wire-less data transmission systems, and to enable exploitation of implicit diversity of multi-path fading channels, both with and without transmitter-end pre-coding. Adaptation properties of per-bin DFE equalization are analyzed by computer simulation for an intermediate number of constituent sub-channels.

Abstract: A crossbar switching fabric comprising a plurality of crossbar input ports and a plurality of crossbar output ports. The traffic from at least one source is directed to more than one of the plurality of crossbar input ports. The traffic from more than one crossbar output port is directed to at least one destination.