Abstract: A specialized Sum-of-Absolute-Difference (SAD) calculator for motion estimation uses inversion rather than 2's complementing. The absolute-value operation of each pixel-pair difference is performed by a bit-wise inversion rather than a complement. This reduces delay since the adder/incrementer propagation is eliminated. The increment needed to adjust for inversion rather than 2's complementing is accomplished by using the carry inputs to the summing and final adders that generate the sum of the absolute differences. When 2-input final adders are used for summing, a total of k−1 adders are used to sum k absolute differences. One additional increment is needed since only k−1 adders are available. A reduced half-adder rather than a full adder is inserted between the summing and final adder for this remaining increment. Propagation of carries between bit positions in a full adder can be avoided using the half adder.

Abstract: Disclosed is a texture prefetching method for use in a three-dimensional graphics display system in which texture maps of an object are stored in memory for texels at (u,v) memory locations. The method of fetching texels for use in calculating (x,y) display pixel values comprises the steps of: a) identifying in (u,v) space a geometric shape to be displayed in (x,y) space, b) establishing tiles of pixels within the geometric shape for use in accessing texels, c) computing texel addresses at one side of a tile based on current addresses (topuc, topvc) and first and second derivatives of (u,v) as a function of (x) and a first derivative as a function of (y), d) computing texel addresses at an opposing side of the tile based on current addresses (u0,v0) and first and second derivatives of (u,v) as a function of (x) and a first derivative as a function of (y), and e) fetching texel blocks within the tiles as defined by the addresses in steps c) and d).

Abstract: A store-and-forward network switch uses an embedded dynamic-random-access memory (DRAM) packet memory. An input port controller receiving a packet writes the packet to the embedded packet memory. The input port controller then sends a message to the output port over an internal token bus. The message includes the row address in the embedded packet memory where the packet was written and its length. The output port reads the message and reads the packet from the embedded memory at the row address before transmitting the packet to external media. Packets are stored at row boundaries so that DRAM page-mode cycles predominate. Only one packet is written to each DRAM row or page. Thus the column address is not sent between ports with the message sent over the token bus. A routing table can also be included in the embedded DRAM.

Abstract: Digital-video compression uses motion vectors to encode movement of macroblocks from one image to another image in a sequence of images. Motion vectors are estimated using multiple levels of a picture, with higher levels having lower resolutions. Such hierarchical or pyramid motion estimation generates lower-resolution pictures from the full-resolution picture. A selected macroblock in a reference picture is compared to ranges in each successively-higher-resolution level. Rather than store the levels of a picture as full pixels, only a luminance Y component of a YUV pixel is stored and used for motion estimation. Further memory savings is achieved by reducing the width of the Y pixels from 8 bits to 6 bits for the top and bottom levels, and to 4 bits for intermediate levels of the picture. Pixels are reduced in width by storing only the most-significant-bits (MSBs), or by dithering. Motion estimation searches in each level are performed using pictures with reduced-width pixels.

Abstract: A multimedia notebook or laptop personal computer (PC) has an enhanced audio system. An external audio controller in a docking station is connected to the laptop PC's audio system using a digital-audio link. The digital-audio link uses digital signals that have high noise immunity. The high noise immunity allows the digital-audio signals to be routed through the inexpensive docking connector, which has many other noisy, high-speed signals. Dedicated, expensive, noise-prone, and difficult-to-connect analog-audio connectors between the laptop PC and the docking station are eliminated. Analog-digital converter audio CODEC's are placed in both the docking station and in the laptop PC. A master mixer in the laptop PC mixes digital audio from the external audio controller in the docking station with digital audio from an external audio controller inside the laptop PC. The master mixer also connects to a zoom-video audio port and to an internal PCI bus for storing and retrieving audio clips.

Abstract: A search engine for a network switch reads a routing table for an entry with a matching MAC or IP address. The routing table is contained in an embedded DRAM. The search engine and the embedded-DRAM routing table are integrated together on the same integrated circuit chip, allowing a very wide data path between the search engine and the routing table. A free-running sequencer outputs addresses to the routing table so that each entry is read in a continuous-loop sequence. The same entry is sent to comparators for all active searches. Destination addresses for different input ports are compared to the entry read from the table. A match ends the search for a port while searches for other ports continue. Since ports can begin and end searches at any point in the continuous-loop sequence, a same low latency is provided for all input ports, even when other searches are in progress. The wide data path from the embedded-DRAM allows several entries to be read and compared for each cycle and for each port.

Abstract: A phase detector determines a phase error value dependent on the relative phase between a local oscillator signal, used for the system clock, and an input signal received over a PR (a, b, b, a) channel. The error value is used to lock the phase and frequency of an input signal to the phase and frequency of the clock in a phase-lock loop (FIG. 1, not shown). The input signal is sampled at regular intervals in accordance with the local oscillator signal, and the sampled values provided on a line 10. A threshold slicer 22 selects an ideal sample value for a sampling point by comparing the sampled values with thresholds received on threshold inputs 23 to 26. A subtracter 32 determines a difference value which corresponds to a difference between the ideal sample value and the actual sample value for that sampling point. A subtracter 28 and a delay register 29 operate to determine the sense of change to the ideal sample value from a ideal sample value for a preceding sampling point.

Abstract: A graphics system includes an accelerated graphics port (AGP) bus to the graphics accelerator. The graphics accelerator includes a 3D-graphics engine that renders textures, and a local graphics memory. Preferably, the local graphics memory is an embedded DRAM on the graphics-accelerator chip. A portion of the personal computer's main memory is set aside as an AGP memory for storing textures for 3D-graphics rendering. High-level application programs create textures in the AGP memory. A 3D graphics software driver that controls the graphics accelerator manages a texture cache in the local graphics memory. When the high-level application requests that the 3D graphics driver render a texture in the AGP memory, the 3D graphics driver moves the texture to the texture cache. Once the texture has been copied from the AGP memory, over the AGP bus to the texture cache in the local graphics memory, the 3D graphics engine begins rendering the texture.

Abstract: Copy protection support is added to the display driver in a laptop PC. Laptop PCs without any copy protection facilitate illegal copying of optical disks such as digital-versatile disk (DVD), since some laptop PCs now include a TV encoder (scan-line converter) that converts the computer-generated formats such as SVGA to TV formats such as NTSC and PAL. While VCRs cannot make copies of computer formats such as SVGA, a VCR connected to the laptop PCs TV-encoder output can make an illegal videocassette copy of a DVD title. The portability of laptop PCs makes them particularly attractive to video thieves. Some PCs are being equipped with TV encoders with advanced copy-protection features such as MacroVision encoders. The video BIOS determines if the TV encoder is MacroVision compliant and is queried by the display driver when a DVD navigator or player requests MacroVision encoding.

Abstract: A reciprocal generator is useful for perspective correction for 3D graphics. The input range is divided into many sections. A lookup table contains reciprocal outputs for only two of the sections, the smallest-inputs section and the largest-inputs section. Entries in the table for the smallest section contain a base and a scale factor to indicate the reciprocal value. One entry is provided for each possible input value in the smallest section. This provides high precision where the outputs have the largest values, reducing visible distortions caused by relatively small changes in the large output values. Each section is divided into intervals, with one table entry for each interval. For the largest section, each table entry has an initial reciprocal and a slope of a line approximating the reciprocal curve in that interval. Reciprocals for inputs within the interval are calculated by multiplying an offset into the interval by the slope, and then adding to the initial reciprocal for that interval.

Abstract: A net sample is added or removed from an audio sample stream by fading in or out fractional samples over many sample periods. A sample-rate converter has a FIFO that is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by removing one net sample over many sample periods. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by adding one net sample over many sample periods.

Abstract: A digital-to-analog converter (DEC) is useful for driving both SVGA display monitors and NTSC TV monitors. The DAC converts 8-bit digital signals to analog voltage for SVGA, but converts 9-bit signals to a wider range of analog voltages for NTSC. Instead of doubling a number of current sources from 255 to 511 for 9-bit conversions, a single least-significant-bit (LSB) current source is added for 9-bit mode. The LSB current source adds one-half of the current that the other current sources do. The LSB current source is disabled for 8-bit mode. The current from the other current sources is doubled for 9-bit mode by adjusting the bias voltage. The bias voltage for p-channel transistors in all the current sources is lowered for 9-bit mode by a bias generator. The bias generator compares a voltage across an external resistor to a band-gap reference and adjusts the bias voltage until the voltage drop across the resistor matches the band-gap reference.

Abstract: A 3D graphics processor has parallel triangle pixel pipelines. One or more triangle setup engine(s) receives triangle primitives from a host or geometry engine and generates vertex color, texture and other attributes as well as their gradients. The triangle setup engine makes available all required triangle data to the triangle pixel pipelines. The triangle pixel pipelines accept the next triangle data on a demand basis, when finished with the previous triangle. Each triangle pixel pipeline has a span engine that generates endpoints along the 3 edges of the triangle where the horizontal lines (spans) intersect. Each triangle pixel pipeline also has a raster engine that receives the endpoints as well as gradients and generates color, texture and other attributes for each pixel along a span between endpoints. The raster engine then composites pixels from these attributes and updates visible pixels in the frame buffer.

Abstract: A cascaded multimedia arbiter and method for arbitrating access to a shared multimedia memory, which is used to store multiple frame buffers for multiple monitors. Other buffers for multimedia agents such as for audio, camera input, digital-versatile disk (DVD) input, and three dimensional (3D) rendering share the same memory. The shared memory allows flexible memory allocation as graphics, audio, and multimedia modes change. Many real-time agents such as for graphics and audio read the memory to fill first-in-first-out (FIFO) buffers. These real-time agents are assigned a fixed slot in a round-robin arbitration. The last or final arbitration slot is used by all non-real-time agents, such as the host, 3D engine, and DVD playback. These non-real-time agents can wait, but need the most bandwidth to maximize performance. The last time slot uses a priority arbiter to grant access in a priority order to the non-real-time agents.

Abstract: A content-addressable memory (CAM) cell uses only n-channel (NMOS) transistors. A total of six transistors (6T) are used in the cell. Dynamic storage and differential sensing are used. A pair of bit lines carry true and complement data. A word line connected to the gates of pass transistors couples the bit lines to gates of storage transistors. The sources of the storage transistors are grounded. Charge is dynamically stored on the gates of the storage transistors when the pass transistors are turned off. One storage transistor has a gate charged to a high voltage and is thus on, while the other storage transistor has its gate discharged to a low voltage and is thus off. The drains of the storage transistors are connected to a match line through a pair of match transistors. The gates of the match transistors are connected to the bit lines. During a compare operation, the test data and its complement are applied to the bit lines, turning one of the match transistors on and the other off.

Abstract: A controller chip has programmable registers that control the operation of the controller chip. The controller chip connects to a microprocessor and bus controller through a bus that performs burst cycles. Although only one address (the starting address) is sent over the bus during the burst cycle, multiple data words are sent in the burst. These data words are written to addresses that follow the starting address in a fixed burst sequence. Programmable registers are accessed in an order that is not the fixed burst sequence. The programmable registers are accessed in a non-sequential order in a single burst cycle by using a mapping control word. The starting address is is set to the address of a mapping control register in the controller chip. The mapping control word is sent as the first data word after the starting address. The mapping control word is decoded to determine which of the programmable registers are to be written during the burst cycle.

Abstract: Indexed registers in controller chips are read in a two-step process. First, an 8-bit write instruction writes an index into an index register in the controller chip. Secondly, a 16-bit read instruction reads both the index register and a data register selected by the index from the index register. When index registers are read in a multi-threaded system, programs in two different threads could access the same index register, each writing a different index into the index register. When another thread over-writes an index written by a current thread, the wrong index and the wrong data are read by the current thread. The current thread detects that the index was overwritten by another thread by extracting the index from the 16-bit read and comparing it to the desired index. When the extracted index mis-matches, the current thread retries, again writing the index and reading back both the index and data.

Abstract: A 3D-graphics engine has several texture maps with different levels of detail (LOD). The largest of the four derivatives of the u,v texture-map coordinates with respect to the x,y screen coordinates determines which LOD texture map to select. Using bi-linear interpolation, the four nearest texture pixels or texels are fetched from the texture map in a texture memory and a weighted-average texel generated. Distortion in space and time can be visible when a triangle transitions from one LOD texture map to the next LOD map. Tri-linear interpolation eliminates this LOD-transitioning distortion by generating weighted-average texels for both the LOD map and for four texels from a next LOD map. Unfortunately the calculational complexity is more than doubled for tri-linear rather than bi-linear interpolation. Tri-linear interpolation is employed only near a transition to a next LOD map. When the derivatives are not near an LOD-map transition, only bi-linear interpolation is performed.

Abstract: An embedded DRAM is incorporated inside a digital-versatile-disk (DVD) playback-controller integrated circuit. Data from the DVD optical disk is written to a data block in the embedded DRAM. Error correction is performed by reading the data block to generate syndromes and over-writing errors in the data block with corrections. Once the data block is corrected, it is copied or moved to a different area of the embedded memory, a host-buffer area. As the data block is moved, de-scrambling is performed to decrypt the data. The re-ordered data is stripped of overhead such as ECC bytes and written to the host-buffer area of the embedded DRAM. A checksum is generated as the data is moved, and the checksum is compared to a stored checksum to ensure that all errors were corrected. The data block in the host-buffer area is then transferred to a host. The embedded DRAM has a very wide data-access width of 16 bytes.

Abstract: A digital-versatile disk (DVD) playback-controller integrated circuit (IC) writes data to a block in an embedded DRAM memory. The memory block has rows and columns. Data read from a DVD optical disk is read in row order. Rather than write the DVD data across the rows in the memory block, the DVD data is accumulated into 16-byte words, and successive 16-byte words are written down a column in the memory block. Each row from the DVD disk is written to a 16-byte-wide column in the memory block. The embedded DRAM has a wide 16-byte interface, so all 16 bytes in a word are written during a single memory-access cycle. All the bytes in the memory block must be read in column-order for column-syndrome generation. Since the row-column ordering is reversed, the column-syndrome generator reads bytes across the memory-block rows. Most of these fetches are DRAM page hits, so access speed is improved for column-syndrome generation.