Abstract: A graphics controller system which has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals, all in the form of a CMOS integrated circuit. The video memory is integrated on the same integrated circuit as the graphics controller; no package pins are required for the memory interface. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A graphics controller system which has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals, all in the form of a CMOS integrated circuit. The video memory is integrated on the same integrated circuit as the graphics controller; no package pins are required for the memory interface. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A CMOS integrated circuit which has a graphics controller system that has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with package pin connections.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A graphics controller system which has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals, all in the form of a CMOS integrated circuit. The video memory is integrated on the same integrated circuit as the graphics controller; no package pins are required for the memory interface.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: Systems and methods are described for distributed DRAM refreshing. A method of distributed DRAM refreshing includes: refreshing a first row of memory cells in a first array of DRAM memory cells with a first row of sense amplifiers; and then refreshing a second row of memory cells in a second array of DRAM memory cells with a second row of sense amplifiers. The systems and methods provide advantages in that magnitude of power transients (noise) can be reduced. In addition, the performance can be improved when the arrays are arranged in multiple sub-groups.

Abstract: A circuit system for generating phase values and frame counts, particularly adapted for liquid crystal displays is described. The phase values are generated by 8.times.8 matrices, which are formed, in turn, from smaller matrices. The circuit system handles a large number of gray scale levels, 64, which are highly linear in their shading with a reduced possibility of display flicker. Furthermore, the frame count generating circuitry are arranged with respect to the phase values generating circuitry for a highly integrated implementation for color displays.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A method and apparatus for performing memory array/row scoreboarding in a dynamic access memory (DRAM) having dual bank access. The DRAM of the present invention allows dual simultaneous memory accesses into a memory divided into a plurality of arrays (e.g., 48 arrays). Each array of the DRAM contains a plurality of rows (e.g., 256). Each row of the DRAM contains storage for a certain amount of data bits (e.g., 1024). The DRAM in one configuration contains 1.5 Megabytes of memory. During a dual bank DRAM access, the system allows a first access for pre-opening a row (e.g., a page) of DRAM memory within a first array while simultaneously allowing a second access for reading/writing data to an opened row of another array aside from the first array. The present invention scoreboarding system tracks the rows that are currently open so that immediate read/write accesses can take place.

Abstract: A circuit system for generating phase values and frame counts, particularly adapted for liquid crystal displays is described. The phase values are generated by 8.times.8 matrices, which are formed, in turn, from smaller matrices. The circuit system handles a large number of gray scale levels, 64, which are highly linear in their shading with a reduced possibility of display flicker. Furthermore, the frame count generating circuitry are arranged with respect to the phase values generating circuitry for a highly integrated implementation for color displays.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: An object in a video sequence is tracked by object masks generated for frames in the sequence. Macroblocks are motion compensated to predict the new object mask. Large differences between the next frame and the current frame detect suspect regions that may be obscured in the next frame. The motion vectors in the object are clustered using a K-means algorithm. The cluster centroid motion vectors are compared to an average motion vector of each suspect region. When the motion differences are small, the suspect region is considered part of the object and removed from the object mask as an occlusion. Large differences between the prior frame and the current frame detect suspected newly-uncovered regions. The average motion vector of each suspect region is compared to cluster centroid motion vectors. When the motion differences are small, the suspect region is added to the object mask as a disocclusion.