Abstract: Embodiments of apparatus and method for matrix multiplication using processing-in-memory (PIM) are disclosed. In an example, an apparatus for matrix multiplication includes an array of PIM blocks in rows and columns, a controller, and an accumulator. Each PIM block is configured into a computing mode or a memory mode. The controller is configured to divide the array of PIM blocks into a first set of PIM blocks each configured into the memory mode and a second set of PIM blocks each configured into the computing mode. The first set of PIM blocks are configured to store a first matrix, and the second set of PIM blocks are configured to store a second matrix and calculate partial sums of a third matrix based on the first and second matrices. The accumulator is configured to output the third matrix based on the partial sums of the third matrix.

Abstract: The disclosure relates to a low-loss arithmetic circuit, which includes a plurality of arithmetic units, a plurality of storage units, and one or more reset MOSFETs. Each arithmetic unit includes 4 MOSFETs. The disclosure also relates to an operating method of the low-loss arithmetic circuit and a low-loss Processing-in-Memory circuit.

Abstract: Embodiments of apparatus and method for matrix multiplication using processing-in-memory (PIM) are disclosed. In an example, an apparatus for matrix multiplication includes an array of tiles that each include one or more PIM blocks. A PIM block may include a hybrid-mode PIM block that may be configured into a digital mode or an analog mode. The PIM block configured into digital mode may perform operations associated with depth-wise (DW) convolution. On the other hand, a PIM block configured into analog mode may perform operations associated with point-wise (PW) convolution. A controller may be used to configure the PIM block into either digital mode or analog mode, depending on the computations.

Abstract: The disclosure relates to a low-loss arithmetic circuit, which includes a plurality of arithmetic units, a plurality of storage units, and one or more reset MOSFETs. Each arithmetic unit includes 4 MOSFETs. The disclosure also relates to an operating method of the low-loss arithmetic circuit and a low-loss Processing-in-Memory circuit.