Abstract: A system for reducing peaks comprises a processor and a memory. The processor is configured to determine phase offsets for a plurality of input signals. The phase offsets are determined using trials of phase offsets to determine a selected set of phase offsets. The processor is further configured to modulate the input data signals using the selected set of phase offsets to produce modulated phase offset data signals and to generate a sum of modulated phase offset data signals, such that the sum has a lower peak value as compared to the sum not using the selected set of phase offset signals.

Abstract: A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de-sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de-sequencing control commands received from the LCAS control manager.

Abstract: To more fully utilize the available bandwidth of a network link, network nodes in accordance with the present invention allow TDM data to be combined with packet data. A Packet/TDM cross connect switch, having both a TDM switch and a packet switch, is used in these embodiments. Data packets are transformed into TDM packet columns. The TDM packet columns are combined with standard TDM data columns in the payload of a TDM data frame. Data packets may be sorted based on a priority scheme, in which high priority data packets are given precedence over lower priority data. However, both high priority and low priority may be combined in a TDM packet column.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: Transmitter waveform dispersion penalty (“TWDP”) is decreased in a transmitter. A binary data signal is received for transmission over a channel that exhibits TWDP. The data signal is shifted less than a full clock cycle to generate at least one post cursor signal. The post cursor signal is subtracted from the data signal to generate a transmitter output data signal for transmission over the channel. In addition to decreasing TWDP, data dependent jitter is also reduced for data transmission across a channel that exhibits a multi-pole transmission characteristic. A main data signal and at least one cursor signal, which is shifted at least a portion of a clock period from the main data signal, is generated. The cursor signal is filtered to filter out effects based on the second pole of the multi-pole transmission characteristic. The main data signal is subtracted from the filtered cursor signal to generate the transmitter output data signal.

Abstract: A CAM array includes a plurality of regular rows and a reference row. Each regular row is partitioned into a plurality of row segments, with each row segment including a number of CAM cells coupled to a corresponding match line segment. The reference row generates self-timed control signals for corresponding segments of the regular rows. Control circuits selectively enable a respective row segment in response to a logical combination of match results in a previous row segment and an associated one of the self-timed control signals.

Abstract: A system, method, and computer program product are provided for optimal packet flow in a multi-processor system on a chip. In operation, a credit is allocated for each of a plurality of agents coupled to a messaging network, the allocating including reserving one or more entries in a receive queue of at least one of the plurality of agents. Additionally, a first credit is decremented in response to a first agent sending a message to a second agent, the plurality of agents including the first and second agents. Furthermore, one of the first credit or a second credit is incremented in response to a signal from the second agent.

Abstract: A stacked switch using a resilient packet ring protocol comprises a plurality of switch modules coupled to one another in a ring topology and each having a plurality of external terminals for interfacing with external devices. Each switch module includes an external interface for communicating with the external terminals, the external interface configured to communicate using a communication protocol; and an internal interface for communicating with other switches, the internal interface using a resilient packet ring (RPR) protocol. Advantages of the invention include the ability to flexibly create a high performance stacked switch with advanced features.

Abstract: Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.

Abstract: A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic.

Abstract: Quaternary CAM cells are provided that include one or more compare circuits that each has a minimal number of pull-down transistors coupled between the match line and ground potential. For some embodiments, the compare circuit includes two parallel paths between the match line and ground potential, with each parallel path consisting of a single pull-down transistor having a gate selectively coupled to the stored data value in response to a comparand value.

Abstract: A video processing device (150) includes a bitstream accelerator module (106) and a video processing engine (108). The bitstream accelerator module (106) has an input for receiving a stream of encoded video data, and an output adapted to be coupled to a memory (112) for storing partially decoded video data. The bitstream accelerator module (106) partially decodes the stream of encoded video data according to a selected one of a plurality of video formats to provide the partially decoded video data. The video processing engine (108) has input adapted to be coupled to the memory (112) for reading the partially decoded video data, and an output for providing decoded video data.

Abstract: A content addressable memory (CAM) device can include a number of bit lines. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit car have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state prior to, and for a duration of at least of a portion of an access operation.

Abstract: A system and method are provided for sharing data between a network including one or more network nodes. The network includes a number of individual network nodes and a home network node communicating with one another. The individual network nodes and the home network node include a plurality of processors and memory caches. The memory caches consist of private caches corresponding to individual processors, as well as shared caches which are shared among the plurality of processors of an individual node and accessible by the processors of the other network nodes. Each network node is capable of executing a hierarchy of data requests that originate in the private caches of an individual local network node. If no cache hits occur within the local network node, a conditional request is sent to the home network node to request data through the shared caches of the other network nodes.

Abstract: A method and apparatus for ordering a plurality (P) of entries having various prefix lengths for storage in a number (T) of available storage locations in a content addressable memory (CAM) array according to the prefix lengths is disclosed. Initially, a first number (N) of the entries of selected and used to generate a distribution graph of their prefix lengths. Then, for each unique prefix length, a corresponding subset of the T storage locations in the CAM array are allocated according to a predicted prefix length distribution indicated by the distribution graph. Then, all of the entries are stored in the corresponding allocated storage locations according to prefix length.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.

Abstract: A signal processing method includes inputting a digital signal, providing a plurality of coefficients; and determining an output. The output is approximately equal to an aggregate of a plurality of linear reference components, and each of the linear reference components is approximately equal to an aggregate of a corresponding set of digital signal samples that is scaled by the plurality of coefficients.

Abstract: A receiver is optimized by adapting the taps of a decision feedback equalizer component within the receiver. Data decisions and error decisions are generated. These data decision and error decisions are used to derive an error rate of data by measuring the number of margin hits that occur. A balance value is also calculated from the data decisions and the error decisions. The balance value is used to update a tap of the decision feedback equalizer. The updating of the tap continues until the number of margin hits has been minimized.

Abstract: A method and system are described for canceling far end cross-talk in communication systems. A first transmitter transmits the first effective data source signals across the first channel. A second transmitter transmits the second effective data source signals across the second channel. In one embodiment, a receiver unit receives first and second effective data source signals across a first channel and a second channel, respectively, and also one or more cross-talk signals. A far end cross talk (FEXT) canceller located in the receiver unit receives second estimated effective data source signals based on the second effective data source signals. The receiver unit cancels the one or more cross-talk signals using the second estimated effective data source signals.