Abstract: An apparatus for use with a wafer prober and a probe card comprising a stiffening member having a feature defining a first plane. The stiffening member is mountable atop the central portion of the probe card. A reference member is provided to mount to the wafer prober and has an underside with a feature defining a second plane. When the feature of the stiffening member defining the first plane is urged against the feature of the reference member defining a second plane the probe tips of the probe card are substantially planarized relative to the wafer prober.

Abstract: A method and system are provided for programming a plurality of memory devices arranged in parallel. In one embodiment of the present invention, the plurality of memory devices comprises first and second memory devices, and the method comprises providing successively the first address to the first memory device and the second address to the second memory device. The first address refers to a first group of storage locations in the first memory device and the second address refers to a second group of storage locations in the second memory device. The method then proceeds to load in parallel a string of data to the first and second memory devices so that the string of data is written simultaneously to the first group of storage locations in the first memory device and to the second group of storage locations in the second memory device.

Abstract: A system and method for testing multiple smart card devices in parallel and asynchronously are provided. The system includes a smart card module that may be easily inserted in a digital test system. The smart card module includes multiple smart card instrument channels, each one of which testing a separate smart card device independently and asynchronously from the others. The smart card instrument channels employ a novel modulation technique based on palette waveforms that are formed of transitions between two data bits.

Abstract: A tester and method are provided for testing semiconductor devices. Generally, the tester includes a multitasking Algorithmic Pattern Generator (APG) to concurrently execute multiple programs on multiple test sites using a single pattern generator. In one embodiment, up to eight test programs are run independently and concurrently on eight independent sixteen-pin devices on a 128 pin test site. When the multitasking APG is ready to broadcast to a device, timing system associated with that device only (and not the other devices) are loaded. While the timing system is executing the cycle of the test programs for the device just loaded, the APG continues on to load the other devices. Because of the slow cycle rates required for programming versus reading, the tester is particularly advantageous for testing flash memory. Optionally, for higher throughput, the APG can be run in lock step at up to a maximum operating frequency of the APG during read cycle of flash.

Abstract: A tester configured to stack with at least one other tester to provide a test system for simultaneously testing a number of devices in parallel on different testers, or testing a device having more pins than can be accommodated by a single tester. The tester includes a test site with a number of pin electronics channels, an interface for interfacing with the device, and a computer for interfacing with a host computer in the test system. The testers can be fastened directly to one another or to a common frame. Preferably, the interface enables a single device board to simultaneously engage interfaces on multiple testers. More preferably, the interface extends from a top surface of the tester to engage the device board. Vents in top and front surfaces of an enclosure enables movement of air to cool components of the tester without interference from testers on either side or a back of the enclosure.

Abstract: This invention provides a manipulator for positioning a test head relative to a prober or other reference. The manipulator has a frame; a linkage coupled to the frame and including first and second links having freedom of rotation about respective pivots and a third link coupled to the first and second links such that the third link has translational and rotational degrees of freedom of movement; and an adaptor coupled to the third link and configured to attach to a test head. The invention also provides a method of controlling the manipulator.

Abstract: This invention provides a manipulator for positioning a test head relative to a prober or other reference. The manipulator has a frame; a linkage coupled to the frame and including first and second links having freedom of rotation about respective pivots and a third link coupled to the first and second links such that the third link has translational and rotational degrees of freedom of movement; and an adaptor coupled to the third link and configured to attach to a test head. The invention also provides a method of controlling the manipulator.

Abstract: An apparatus for use with a wafer prober and a probe card comprising a stiffening member having a feature defining a first plane. The stiffening member is mountable atop the central portion of the probe card. A reference member is provided to mount to the wafer prober and has an underside with a feature defining a second plane. When the feature of the stiffening member defining the first plane is urged against the feature of the reference member defining a second plane the probe tips of the probe card are substantially planarized relative to the wafer prober.

Abstract: An apparatus for use with a wafer prober and a probe card comprising a stiffening member having a feature defining a first plane. The stiffening member is mountable atop the central portion of the probe card. A reference member is provided to mount to the wafer prober and has an underside with a feature defining a second plane. When the feature of the stiffening member defining the first plane is urged against the feature of the reference member defining a second plane the probe tips of the probe card are substantially planarized relative to the wafer prober.

Abstract: A system and method are provided for testing electronic devices. Generally, the system includes: (i) a pattern memory with outputs for storing and outputting bits to the device; and (ii) a pattern scrambler for coupling bits from the outputs to pins on the device to provide a test pattern to the device having a width of from 1 bit to a width equal to the number of outputs. Preferably, the system includes a clock with a clock cycle, and the scrambler can change the width and/or depth of the test pattern on a cycle-by-cycle basis More preferably, the scrambler can change the bits coupled to one or more of the pins on a cycle-by-cycle basis. In one embodiment, the memory simultaneously provides logic vector memory and scan memory for storing logic and scan vectors respectively, and the width/depth of the vectors can be changed on a cycle-by-cycle basis.

Abstract: A method and apparatus are provided for high speed testing of devices having either logic circuits, memory arrays or both. Apparatus (100) includes: (i) pin electronics (P/Es 145) each coupling the apparatus to one of a number of pins (115) on device (110); (ii) timing and format circuits (T/Fs 150) for mapping a signal to one of P/Es (100); (iii) pattern generator (140) having a number of outputs for outputting signals for testing device (110); (iv) pin scrambling circuit (155) between pattern generator (140) and T/Fs (150), the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any of the T/Fs; and (v) clock (135) for providing a clock signal having a clock cycle to pattern generator (140) and T/Fs (150). T/Fs (150) are capable of switching the signals coupled to P/Es (100) at least twice each clock cycle.