Abstract: A six-degree-of-freedom large-stroke uncoupling large hollow series-parallel piezoelectric micro-motion platform includes a base, a movable platform top, a second platform and a first platform, wherein a first guide unit, a second guide unit, a third guide unit, a fourth guide unit, a fifth guide unit and a sixth guide unit are respectively connected in sequence to the second platform and the first platform; the first guide unit is internally provided with a first drive unit, the second guide unit is internally provided with a second drive unit, and the third guide unit is internally provided with a third drive unit; and the base is provided with a fourth drive unit, a fifth drive unit, a sixth drive unit and a seventh drive unit, the fifth drive unit is provided below the second drive unit, and the sixth drive unit is provided below the third drive unit.

Abstract: The invention discloses a circuit aging detection sensor based on voltage comparison. A control circuit generates an aging voltage signal, a standard voltage signal and a reference voltage signal. The aging voltage signal passes through a first voltage-controlled oscillator to generate an aging frequency signal. The standard voltage signal passes through a second voltage-controlled oscillator to generate a standard frequency signal. The standard frequency signal and the aging frequency signal pass through an aging detection circuit to generate a frequency difference signal. A level signal generated by a serial data detector passes through a beat-frequency oscillator to generate a reset signal. A counter quantizes aging information, which is converted by a digital-analog converter into a quantized voltage signal. The quantized voltage signal is compared with the reference voltage signal by a voltage comparator, to generate a hopping signal at a voltage superposition node, and an aging signal is output.

Abstract: A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

Abstract: The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter.

Abstract: A mass spectrometry system and a working method and an application thereof, and a sampling device. The mass spectrometry system includes an ion source, a sampling device and a mass spectrometer. The sampling device includes: a guide rail; a support adapted to move on the guide rail; a bearing member made from a hydrophobic material with two ends being fixed to the support; a plurality of containers for containing samples arranged on the support; a plurality of transport members made from a hydrophilic material and including a first portion provided on the bearing member and a second portion connected to the first portion and extending into each container; adjacent transport members being not in contact; and a drive module configured to drive the support to move on the guide rail such that a central axis of an exit port of the ion source passes through the first portion.

Abstract: A true random number generator based on a voltage-controlled oscillator includes a thermal noise generator, a ring oscillator, a voltage-controlled oscillator, a D flip-flop, and a post-processing circuit. The D flip-flop has a clock terminal, an input terminal, and an output terminal. An output terminal of the thermal noise generator is connected with an input terminal of the voltage-controlled oscillator. An output terminal of the voltage-controlled oscillator is connected with the clock terminal of the D flip-flop. An output terminal of the ring oscillator is connected with the input terminal of the D flip-flop. The output terminal of the D flip-flop is connected with an input terminal of the post-processing circuit. An input terminal of the thermal noise generator is connected with a reference level. The thermal noise generator includes a digital-analog converter, an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor.

Abstract: A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

Abstract: The invention discloses a circuit aging detection sensor based on voltage comparison. A control circuit generates an aging voltage signal, a standard voltage signal and a reference voltage signal. The aging voltage signal passes through a first voltage-controlled oscillator to generate an aging frequency signal. The standard voltage signal passes through a second voltage-controlled oscillator to generate a standard frequency signal. The standard frequency signal and the aging frequency signal pass through an aging detection circuit to generate a frequency difference signal. A level signal generated by a serial data detector passes through a beat-frequency oscillator to generate a reset signal. A counter quantizes aging information, which is converted by a digital-analog converter into a quantized voltage signal. The quantized voltage signal is compared with the reference voltage signal by a voltage comparator, to generate a hopping signal at a voltage superposition node, and an aging signal is output.

Abstract: A positive feedback XOR/XNOR gate and a low-delay hybrid logic adder are provided. The low-delay hybrid logic adder comprises the positive feedback XOR/XNOR gate and an output circuit. The positive feedback XOR/XNOR gate comprises a first PMOS transistor and a second PMOS transistor used as pass transistors, a first NMOS transistor and a second NMOS transistor constituting a pull-down network, and a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor constituting a positive feedback loop. When an XOR logic output terminal of the positive feedback XOR/XNOR gate is pulled down below a switching threshold of an inverter formed by the third PMOS transistor and the fourth NMOS transistor, the positive feedback loop starts to operate to enable the XOR logic output terminal of the positive feedback XOR/XNOR gate to enter a pull-down phase to be pulled down to a low level to avoid threshold voltage losses.

Abstract: The disclosure discloses a method for defending control flow attacks. When a data processor gives a response to an interrupt routine, a return address and a binary key are input to an encryption circuit to be encrypted to obtain an encrypted return address, and the obtained encrypted return address is synchronously written into a stack of the data processor and an built-in register bank; when the response given to the interrupt routine by the data processor is finished, the encrypted return address is read from the tack of the data processor and the built-in register bank; afterwards, the two encrypted return addresses are decrypted by first and second decryption circuits respectively to obtain two decrypted return addresses; and the two decrypted return addresses are compared to draw a conclusion whether the data process suffers from a control flow attack, and data processor determines to continue or terminate the routine accordingly.

Abstract: A low-profile CTS flat-plate array antenna includes a radiating layer, a mode switching layer and a feed network layer which are sequentially arrayed from top to bottom. The mode switching layer comprises a first metal plate and a mode switching cavity array arranged on an upper surface of the first metal plate and comprising 22n mode switching cavities arrayed in 2n rows and 2n columns, wherein n is an integer greater than or equal to 1. Each mode switching cavity includes a first rectangular cavity, a second rectangular cavity, a third rectangular cavity, a fourth rectangular cavity and a fifth rectangular cavity which are sequentially connected from left to right. The 2n mode switching cavities located in each row are sequentially connected end to end.

Abstract: An ultra-wideband CTS flat-plate array antenna includes a radiating layer, a mode switching layer and a feed network layer sequentially arrayed from top to bottom. The mode switching layer comprises a first metal plate and a mode switching cavity formed in the first metal plate and including two mode switching units which are arranged left and right and each includes eight H-plane Y-type single-ridge waveguide power dividers arrayed in 4 rows and 2 columns. The H-plane Y-type single-ridge waveguide power divider in the mth row and 1st column is bilaterally symmetrical with the H-plane Y-type single-ridge waveguide power divider in the mth row and 2nd column. The two H-plane Y-type single-ridge waveguide power dividers in the each row are connected through an E-plane T-type single-ridge waveguide power divider. A center distance between every two adjacent H-plane Y-type single-ridge waveguide power dividers in each column is not over one wavelength.

Abstract: A six-degree-of-freedom large-stroke uncoupling large hollow series-parallel piezoelectric micro-motion platform includes a base, a movable platform top, a second platform and a first platform, wherein a first guide unit, a second guide unit, a third guide unit, a fourth guide unit, a fifth guide unit and a sixth guide unit are respectively connected in sequence to the second platform and the first platform; the first guide unit is internally provided with a first drive unit, the second guide unit is internally provided with a second drive unit, and the third guide unit is internally provided with a third drive unit; and the base is provided with a fourth drive unit, a fifth drive unit, a sixth drive unit and a seventh drive unit, the fifth drive unit is provided below the second drive unit, and the sixth drive unit is provided below the third drive unit.

Abstract: A true random number generator based on a voltage-controlled oscillator includes a thermal noise generator, a ring oscillator, a voltage-controlled oscillator, a D flip-flop, and a post-processing circuit. The D flip-flop has a clock terminal, an input terminal, and an output terminal. An output terminal of the thermal noise generator is connected with an input terminal of the voltage-controlled oscillator. An output terminal of the voltage-controlled oscillator is connected with the clock terminal of the D flip-flop. An output terminal of the ring oscillator is connected with the input terminal of the D flip-flop. The output terminal of the D flip-flop is connected with an input terminal of the post-processing circuit. An input terminal of the thermal noise generator is connected with a reference level. The thermal noise generator includes a digital-analog converter, an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor.

Abstract: A data selector based on TVD includes two AND gates, an OR gate, and three buffers, wherein the two AND gates and the OR gate adopt a three-phase dual-track pre-charge logic as a work logic. The data selector fulfills one time of evaluation operation and has three stages in one cycle. When a discharge control signal and a pre-charge control signal are at low levels, the data selector enters a pre-charge stage. When an evaluation signal is changed to a high level from a low level, the data selector implements the evaluation operation to fulfill the circuit function. When the discharge control signal is changed to a high level from the low level, the data selector enters a discharge state and gets ready for the next evaluation operation.

Abstract: A data selector based on TVD includes two AND gates, an OR gate, and three buffers, wherein the two AND gates and the OR gate adopt a three-phase dual-track pre-charge logic as a work logic. The data selector fulfills one time of evaluation operation and has three stages in one cycle. When a discharge control signal and a pre-charge control signal are at low levels, the data selector enters a pre-charge stage. When an evaluation signal is changed to a high level from a low level, the data selector implements the evaluation operation to fulfill the circuit function. When the discharge control signal is changed to a high level from the low level, the data selector enters a discharge state and gets ready for the next evaluation operation.

Abstract: A multi-port PUF circuit based on MOSFET current division deviations comprises a reference source, a row decoder, a column decoder, a timing controller and 32 PUF arrays. Each PUF array comprises 512 PUF cells arranged in 128 rows and 4 columns, an arbiter, a 1st inverter, a 2nd inverter, a 3rd inverter, a 4th inverter and eight transmission gates. The reference source is connected to the PUF arrays. The mth output terminal of the row decoder is connected to the mth row selective signal input terminals of the 32 PUF arrays. The jth output terminal of the column decoder is connected to the jth selective signal input terminals of the 32 PUF arrays. The 1st output terminal of the timing controller is connected to the control terminal of the row decoder. The 2nd output terminal of the timing controller is connected to the control terminal of the column decoder. The multi-port PUF circuit has the advantages of small circuit area and low power consumption while ensuring circuit performance.

Abstract: The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter.

Abstract: A high-dimensional data nearest-neighbor query method based on variable-length hash codes is disclosed. Specifically, in this method, hash codes with the same code frequency are taken as a sub-data set, all the sub-data sets are ranked, a compression ratio is set for each sub-data set, the sub-data sets are compressed and trained according to the compression ratios, and hash codes and original codes corresponding to the trained sub-data sets are obtained; the hash code of each trained sub-data sets is copied to obtain multiple replicas, and the original codes and the corresponding replicas are strung to obtain strung hash codes which are integrated to form a final nearest-neighbor query table; and, a query code is obtained, and the nearest-neighbor query table is searched for a nearest-neighbor data set to complete query. The query efficiency and accuracy are greatly improved according to the invention.

Abstract: An electronic impedance tuner comprises an adjusting circuit, N cell tuning circuits identical in structure and a switch controller. The adjusting circuit comprises a first microstrip line, a second microstrip line, a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor and a first PIN diode. Each cell tuning circuit comprises a third microstrip line, a fourth microstrip line, a fourth capacitor, a fifth capacitor, a second PIN diode and a third capacitor. The capacitance Cd of the fourth capacitor meets the condition: 4 ? ? Y s N ? ? ? ? ? f 2 ? ? ? req ? 1 - ? ? req ? 2 ? C d ? Y s ? ? ? f 1 ? ? ? req ? 1 - ? ? req ? 2 . The length d of the third microstrip line meets the condition: ? 1 / 4 ? ( N + 1 ) < d < c 4 ? ? reff ? [ ( C d · Z 0 ) 2 + ( 2 ? ? ? f Bragg ) 2 - C d · Z 0 ] .