Patents Assigned to Novel Crystal Technology, Inc.
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Patent number: 11355594Abstract: A diode includes an n-type semiconductor layer including an n-type Ga2O3-based single crystal, and a p-type semiconductor layer including a p-type semiconductor in which a volume of an amorphous portion is higher than a volume of a crystalline portion. The n-type semiconductor layer and the p-type semiconductor layer form a pn junction.Type: GrantFiled: July 23, 2018Date of Patent: June 7, 2022Assignees: Tamura Corporation, Novel Crystal Technology, Inc.Inventor: Kohei Sasaki
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Publication number: 20220033991Abstract: A single crystal manufacturing apparatus to grow a single crystal upward from a seed crystal, the apparatus including an insulated space thermally insulated from a space outside the single crystal manufacturing apparatus, an induction heating coil placed outside the insulated space, a thermal insulation plate that divides the insulated space into a first space including a crystal growth region to grow the single crystal and a second space above the first space and includes a hole above the crystal growth region, a heating element that is placed in the second space and generates heat by induction heating using the induction heating coil to heat the inside of the insulated space, and a support shaft to vertically movably support the seed crystal from below.Type: ApplicationFiled: July 26, 2021Publication date: February 3, 2022Applicant: NOVEL CRYSTAL TECHNOLOGY, INC.Inventor: Kimiyoshi KOSHI
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Publication number: 20210313434Abstract: A semiconductor substrate includes a gallium oxide-based semiconductor single crystal and a chamfered portion at an outer periphery portion. The chamfered portion includes a first inclined surface located on the outer side of a first principal surface of the semiconductor substrate and being linear at an edge in a vertical cross section of the semiconductor substrate, a second inclined surface located on the outer side of a second principal surface on the opposite side to the first principal surface and being linear at an edge in the vertical cross section, and an end face located between the first inclined surface and the second inclined surface at a leading end of the chamfered portion. A width of the end face in a thickness direction of the semiconductor substrate is within the range of not less than 50% and not more than 97% of a thickness of the semiconductor substrate.Type: ApplicationFiled: March 30, 2021Publication date: October 7, 2021Applicant: NOVEL CRYSTAL TECHNOLOGY, INC.Inventors: Shinya WATANABE, Masanori YOKOO
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Publication number: 20210273060Abstract: A field-effect transistor includes a Ga2O3-based semiconductor layer, a source region and a drain region that are formed inside the Ga2O3-based semiconductor layer, a gate electrode that is formed, via a gate insulating film, on a channel region as the Ga2O3-based semiconductor layer between the source region and the drain region, a source electrode connected to the source region, and a drain electrode connected to the drain region. An interface charge including a negative charge is formed between the gate electrode and the channel region, and a gate threshold voltage is not less than 4.5V.Type: ApplicationFiled: February 26, 2021Publication date: September 2, 2021Applicant: Novel Crystal Technology, Inc.Inventors: Tadashi KASE, Kazuo AOKI, Shigenobu YAMAKOSHI, Yuki UCHIDA
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Publication number: 20210269941Abstract: A gallium oxide crystal manufacturing device includes a crucible to hold a gallium oxide source material therein, a crucible support that supports the crucible from below, a crucible support shaft that is connected to the crucible support from below and vertically movably supports the crucible and the crucible support, a tubular furnace core tube that surrounds the crucible, the crucible support and the crucible support shaft, a tubular furnace inner tube that surrounds the furnace core tube, and a resistive heating element including a heat-generating portion placed in a space between the furnace core tube and the furnace inner tube. Melting points of the furnace core tube and the furnace inner tube are not less than 1900° C. A thermal conductivity of a portion of the furnace core tube located directly next to the crucible in a radial direction thereof is higher than a thermal conductivity of the furnace inner tube.Type: ApplicationFiled: February 24, 2021Publication date: September 2, 2021Applicants: Fujikoshi Machinery Corp., SHINSHU UNIVERSITY, Novel Crystal Technology, Inc.Inventors: Keigo HOSHIKAWA, Takumi KOBAYASHI, Yoshio OTSUKA, Toshinori TAISHI
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Patent number: 11081598Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering an inner surface of the trench, and a trench MOS gate that is buried in the trench so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes a lower layer on a side of the first semiconductor layer and an upper layer on a side of the anode electrode having a higher donor concentration than the lower layer.Type: GrantFiled: February 27, 2018Date of Patent: August 3, 2021Assignees: TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.Inventors: Kohei Sasaki, Masataka Higashiwaki
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Patent number: 11043602Abstract: Provided is a Schottky barrier diode which is configured from a Ga2O3-based semiconductor, and has a lower rising voltage than a conventional one. In one embodiment, the Schottky barrier diode 1 is provided which has: a semiconductor layer 10 configured from a Ga2O3-based single crystal; an anode electrode 11 which forms a Schottky junction with the semiconductor layer 10, and has a portion which contacts the semiconductor layer 10 and is composed of Fe or Cu; and a cathode electrode 12.Type: GrantFiled: February 19, 2018Date of Patent: June 22, 2021Assignees: Tamura Corporation, Novel Crystal Technology, Inc.Inventors: Kohei Sasaki, Daiki Wakimoto, Yuki Koishikawa, Quang Tu Thieu
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Publication number: 20210151611Abstract: A Schottky barrier diode includes a semiconductor layer including a Ga2O3-based single crystal, an anode electrode that forms a Schottky junction with the semiconductor layer and is configured so that a portion in contact with the semiconductor layer includes Mo or W, and a cathode electrode. A turn-on voltage thereof is not less than 0.3 V and not more than 0.5 V.Type: ApplicationFiled: June 12, 2018Publication date: May 20, 2021Applicants: TAMURA CORPORATION, Novel Crystal Technology, Inc.Inventors: Kohei SASAKI, Daiki WAKIMOTO, Yuki KOISHIKAWA, Quang Tu THIEU
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Patent number: 11011653Abstract: Provided is a Schottky barrier diode which is configured from a Ga2O3-based semiconductor, and has a lower rising voltage than a conventional one. In one embodiment, the Schottky barrier diode 1 is provided which has: a semiconductor layer 10 configured from a Ga2O3-based single crystal; an anode electrode 11 which forms a Schottky junction with the semiconductor layer 10, and has a portion which contacts the semiconductor layer 10 and is composed of Fe or Cu; and a cathode electrode 12.Type: GrantFiled: February 19, 2018Date of Patent: May 18, 2021Assignees: Tamura Corporation, Novel Crystal Technology, Inc.Inventors: Kohei Sasaki, Daiki Wakimoto, Yuki Koishikawa, Quang Tu Thieu
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Publication number: 20210020789Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer stacked on the first semiconductor layer, includes a Ga2O3-based single crystal, and includes a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench electrode that is buried in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes an insulating dry-etching-damaged layer with a thickness of not more than 0.8 ?m in a region including the inner surface of the trench.Type: ApplicationFiled: February 25, 2019Publication date: January 21, 2021Applicants: TAMURA CORPORATION, Novel Crystal Technology, Inc., TDK CorporationInventors: Kohei SASAKI, Minoru FUJITA, Jun HIRABAYASHI, Jun ARIMA
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Publication number: 20200235234Abstract: A field-effect transistor includes an n-type semiconductor layer that includes a Ga2O3-based single crystal and a plurality of trenches opening on one surface, a gate electrode buried in each of the plurality of trenches, a source electrode connected to a mesa-shaped region between adjacent trenches in the n-type semiconductor layer, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on an opposite side to the source electrode.Type: ApplicationFiled: September 26, 2018Publication date: July 23, 2020Applicants: TAMURA CORPORATION, Novel Crystal Technology, Inc.Inventor: Kohei SASAKI
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Publication number: 20200168711Abstract: A diode includes an n-type semiconductor layer including an n-type Ga2O3-based single crystal, and a p-type semiconductor layer including a p-type semiconductor in which a volume of an amorphous portion is higher than a volume of a crystalline portion. The n-type semiconductor layer and the p-type semiconductor layer form a pn junction.Type: ApplicationFiled: July 23, 2018Publication date: May 28, 2020Applicants: TAMURA CORPORATION, Novel Crystal Technology, Inc.Inventor: Kohei SASAKI
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Publication number: 20200144377Abstract: A Ga2O3-based semiconductor device includes a Ga2O3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga2O3-based crystal layer.Type: ApplicationFiled: April 26, 2018Publication date: May 7, 2020Applicants: NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.Inventors: Masataka HIGASHIWAKI, Yoshiaki NAKATA, Takafumi KAMIMURA, Man Hoi WONG, Kohei SASAKI, Daiki WAKIMOTO
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Publication number: 20200066921Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering an inner surface of the trench, and a trench MOS gate that is buried in the trench so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes a lower layer on a side of the first semiconductor layer and an upper layer on a side of the anode electrode having a higher donor concentration than the lower layer.Type: ApplicationFiled: February 27, 2018Publication date: February 27, 2020Applicants: TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.Inventors: Kohei SASAKI, Masataka HIGASHIWAKI
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Publication number: 20190363197Abstract: Provided is a Schottky barrier diode which is configured from a Ga2O3-based semiconductor, and has a lower rising voltage than a conventional one. In one embodiment, the Schottky barrier diode 1 is provided which has: a semiconductor layer 10 configured from a Ga2O3-based single crystal; an anode electrode 11 which forms a Schottky junction with the semiconductor layer 10, and has a portion which contacts the semiconductor layer 10 and is composed of Fe or Cu; and a cathode electrode 12.Type: ApplicationFiled: February 19, 2018Publication date: November 28, 2019Applicants: TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.Inventors: Kohei SASAKI, Daiki WAKIMOTO, Yuki KOISHIKAWA, Quang Tu THIEU
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Patent number: 10358742Abstract: A method of growing a conductive Ga2O3-based crystal film by MBE includes producing a Ga vapor and a Si-containing vapor and supplying the vapors as molecular beams onto a surface of a Ga2O3-based crystal substrate so as to grow the Ga2O3-based crystal film. The Ga2O3-based crystal film includes a Si-containing Ga2O3-based single crystal film. The Si-containing vapor is produced by heating Si or a Si compound and Ga while allowing the Si or a Si compound to contact with the Ga.Type: GrantFiled: June 2, 2017Date of Patent: July 23, 2019Assignees: TAMURA CORPORATION, Novel Crystal Technology, Inc.Inventors: Kohei Sasaki, Daiki Wakimoto