Abstract: A method and processor to evaluate a monotonicity of a set of input values is disclosed. The processor achieves high processing power by means of an arbitrary number of identical parallel processing elements. Each processing element allows instruction dependent data paths and makes use of ALU factories which consist of a number of separate arithmetic logical units (ALUs) are arranged in a special kind of matrix. The processor allows parallel evaluation and analysis of the monotonicity of a multitude of sets of values. A threshold value can be freely configured to allow an uncertainty of nearly equal values which is of high importance in digital signal processing.

Abstract: A method and apparatus to permute a given set of elements utilizing a permutation network which uses nodes and edges. The permutation network is a minimal network where each of the nodes except the input nodes has N+1 inputs and each of the nodes except the output nodes has N+1 outputs. Generation of any permutation of the provided input elements is allowed; permutations can even comprise copies of elements if desired. The network is characterized that for each output element at least two paths through the network to each input element exist and that each node can only process one element at a time.

Abstract: A method and processor to encode and/or decode a video stream exploiting frame-level parallelism. Frames of the video stream are encoded and/or decoded using M processing units where each processing unit processes one different frame at a time. Each processing unit writes the reconstructed frame to a frame buffer. A processing unit can start the encoding and/or decoding process once sufficient data of the previous reconstructed frame are available.

Abstract: A method and apparatus to control execution of nested loops is disclosed. The method and apparatus stores the loop level of a current loop in execution and uses this loop level to manage a data set provided for each loop. The data set for each loop includes a start address, an end address, and a loop counter or a loop flag, respectively. The method and apparatus allows arbitrary nested loops to be controlled without increasing a complexity level of the circuit and allows additional loop control. The only precondition is that the loop end addresses are different.

Abstract: A method and apparatus for replacement in a least-recently-used strategies is disclosed. An exemplary embodiment of the replacement strategy presented herein is a replacement strategy for set associative caches. The method and apparatus stores a priority level to determine which block frame is to be selected for replacement. Due to its simplicity, the disclosed approach and apparatus enables small implementations and is easily scalable. Consequently, the present method and apparatus is highly desirable for implementations of area critical applications.

Abstract: A timing recovery method is presented which enables time recovery of multi-level PAM signals at baud rate. The method uses a fixed A/D clock, a digital interpolator to re-synchronize incoming samples; a timing phase detector; a loop filter and a numerically controlled oscillator (NCO), controlling re-synchronization of incoming samples within the interpolator. The usage of a Farrow interpolator and a multi-level PAM timing phase detector allows a reduced complexity of the time recovery circuit and a free running clock to the A/D converter.