Patents Assigned to Orca Systems, Inc.
  • Patent number: 7979046
    Abstract: A digital communication circuit can be implemented can be implemented in a CMOS, or other IC structure. The digital circuit can utilize negative frequency removers or image frequency removers in the digital domain. The circuit can include mixers, switches, a complex filter, a low noise amplifier and summers. The image frequency can be removed digitally.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: July 12, 2011
    Assignee: Orca Systems, Inc.
    Inventor: Guruswami Sridharan
  • Patent number: 7898345
    Abstract: A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: March 1, 2011
    Assignee: Orca Systems, Inc.
    Inventor: Kartik M. Sridharan
  • Patent number: 7519349
    Abstract: A digital communication circuit can be implemented can be implemented in a CMOS, or other IC structure. The digital circuit can utilize negative frequency removers or image frequency removers in the digital domain. The circuit can include mixers, switches, a complex filter, a low noise amplifier and summers. The image frequency can be removed digitally.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: April 14, 2009
    Assignee: ORCA Systems, Inc.
    Inventor: Guruswami Sridharan
  • Patent number: 7482885
    Abstract: A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: January 27, 2009
    Assignee: Orca Systems, Inc.
    Inventor: Kartik M. Sridharan