Patents Assigned to Pac Tech-Packaging Technologies GmbH
  • Patent number: 6394158
    Abstract: A method for the thermal connection of overlapping connecting surfaces (19, 20) of two substrates (17, 18), at least one substrate (18) being 5 transparent and laser energy being applied to the connecting surfaces (19, 20) from a rear side (26) of the transparent substrate (18), laser energy being applied separately to each of the contact pairs (37) constructed between two connecting surfaces (19, 20) of the opposing substrates (17, 18).
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: May 28, 2002
    Assignee: Pac Tech Packaging Technologies GmbH
    Inventor: Kaveh Momeni
  • Publication number: 20020040923
    Abstract: A contact structure (10) and a process for producing a contact structure are provided for connecting two substrates (11, 12). The process includes applying solder material (23) to terminal areas (16) of a first substrate (11) to form spacing metallizations (19), and bonding of the first substrate (11) with a second substrate (12). The bonding between the terminal areas (16) of the first substrate (11) and a contact surface area of the second substrate (12) is performed by means of an electrically conductive adhesive compound (20).
    Type: Application
    Filed: December 13, 2001
    Publication date: April 11, 2002
    Applicant: Pac Tech-Packaging Technologies GmbH
    Inventors: Jurgen Schredl, Thomas Oppert
  • Publication number: 20020009828
    Abstract: Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to assigned conducting paths (23) of a conducting-path structure (24, 25) arranged on at least one carrier substrate (21, 22) by the chips being arranged transverse to the longitudinal extent of the carrier substrate.
    Type: Application
    Filed: September 24, 2001
    Publication date: January 24, 2002
    Applicant: PAC TECH - PACKAGING TECHNOLOGIES GMBH
    Inventors: Hans-Hermann Oppermann, Elke Zakel, Ghassem Azdasht, Paul Kasulke
  • Patent number: 6335626
    Abstract: A method and device are provided for determining a parameter for the reproducible production of raised contact metallizations (24, 25) on terminal areas of a substrate. Metallization material is deposited in a metallization bath. A test substrate is employed having at least two terminal areas adjacent at a defined spacing. The substrate is introduced into the metallization bath (10) and the parameter is determined from the variation in an electrical quantity as a consequence of an electrical contact resulting to from the deposition of the metallization material for building up the contact metallizations (24, 25) on the adjacent terminal areas.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: January 1, 2002
    Assignee: Pac Tech - Packaging Technologies GmbH
    Inventor: Gerald Motulla
  • Patent number: 6328200
    Abstract: Process for the selective formation of contact metallisations on terminal areas of a substrate, wherein the surface of the substrate is covered with a template in such a way that template openings forming deposit spaces are arranged above the terminal areas, and wherein the deposit spaces are filled with a solder material, and fusing of the solder material is effected with a view to forming the contact metallisations in the deposit spaces which are non-wettable at least in regions of contact with the solder material.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: December 11, 2001
    Assignee: PAC Tech - Packaging Technologies GmbH
    Inventors: Jürgen Schredl, Paul Kasulke
  • Patent number: 6281577
    Abstract: Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to assigned conducting paths (23) of a conducting-path structure (24, 25) arranged on at least one carrier substrate (21, 22) by the chips being arranged either transverse to the longitudinal extent of the carrier substrate or parallel to the longitudinal extent of the flexibly constructed carrier substrate, as well as a spatial chip arrangement that is formed by means of this process.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: August 28, 2001
    Assignee: PAC Tech-Packaging Technologies GmbH
    Inventors: Hans-Hermann Oppermann, Elke Zakel, Ghassem Azdasht, Paul Kasulke
  • Patent number: 6119919
    Abstract: Method for repairing defective soldered joints, in which in a first method step a soldering material handling device is placed with a soldering material removal device at a soldering material defect point and a defective soldering material deposit is loosened from the connection with a soldering material carrier and removed, and in which in a second method step a soldering material unit from a soldering material application device of the soldering material handling device is applied to the soldering material carrier and connected to the soldering material carrier, the application device being placed at the soldering material defect point.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: September 19, 2000
    Assignee: Pac Tech - Packaging Technologies GmbH
    Inventor: Paul Kasulke
  • Patent number: 6056188
    Abstract: A method of attaching an electronic component to a surface of a plate-shaped support member has as a first step the step of applying the electronic component to the surface of the support member, a solder being arranged between the electronic component and the support member. Following this, a glass fiber or a glass fiber bundle is applied to the surface of the plate-shaped support member located opposite the electronic component. Finally, a laser pulse is conducted through the glass fiber or glass fiber bundle for melting the solder so as to establish a punctiform electrical and mechanical connection between the support member and the electronic component in this way.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: May 2, 2000
    Assignee: Pac Tech-Packaging Technologies GmbH
    Inventors: Ghassem Azdasht, Paul Kasulke
  • Patent number: 5989993
    Abstract: Method for the preparation of electrodeposited or galvanically deposited bumps for the bonding of integrated circuits, characterized by two subsequent metal depositions, deposited without an external current source (chemical metal deposition) on a metallization 1, the first deposition being thicker than the second and the second deposition being more even or more regular throughout a large area than the first one.
    Type: Grant
    Filed: April 22, 1996
    Date of Patent: November 23, 1999
    Assignees: Elke Zakel, Pac Tech Packaging Technologies, GmbH
    Inventors: Elke Zakel, Rolf Aschenbrenner, Andreas Ostmann, Paul Kasulke