Abstract: A data processing system includes the data processing apparatuses formed with the VUPU architecture by combining a general-purpose data processing unit and a special-purpose data processing unit equipped with a data path unit for specialized data processing that is executed according to special-purpose instructions, and equipping the general-purpose data processing unit with a communication function for communicating with the general-purpose data processing unit in another data processing apparatus. In this invention, these data processing apparatuses are combined to form the system with plurality of specialized circuits, therefore, the data processing system in which parallel processing is performed by a plurality of specialized circuits can be provided economically and in a short time.

Abstract: A data processing system includes a general-purpose data processing unit (PU) including an instruction issuing unit that fetches and decodes an instruction in a program and issues the instruction and an execution unit that executes general-purpose processing according to a general-purpose instruction in the program; a special-purpose data processing unit (VU), including a data path unit for special-purpose data processing, that executes special-purpose data processing according to a special-purpose instruction in the program; and a first clock supply unit for stopping, based on a wait signal that is issued by the VU and shows that the PU is waiting for processing of the VU, a first clock signal for a part of the PU.

Abstract: A data processing system is provided that comprises a special-purpose processing unit (VU), a general-purpose processing unit that is suited to general-purpose data processing unit (PU) and a fetch unit for supplying a special-purpose instruction to the VU and supplying a general-purpose instruction to the PU, wherein the PU is equipped with a first mode for operating based on a first instruction from the fetch unit and a second mode for operating based on a second instruction from the VU. The resources of the PU are made available for use by the VU so that the resources of the PU can be used by the VU with effectively no overheads being required by the transfer of data between the VU and the PU. As a result, a processor with even greater flexibility and faster processing can be provided.

Abstract: The control unit of this invention has a microcode control system or systems for special purpose circuit suitable for specific data processing and a microcode control system for general purpose separately. In addition, the control unit has a fetch unit common for the above control systems. Therefore, in the data processing system having the control unit of this invention, the general purpose process and the process using the special purpose circuit, which is different from the general purpose process, are multiply executed, and synchronizing of this multiprocessing is solved in a instruction level.