Patents Assigned to PACKAGING SIP
  • Process for the wafer-scale fabrication of hermetic electronic modules
    Patent number: 10483180
    Abstract: An electronic module including one or more electronic components that are electrically connected to a multilayer PCB circuit comprises, on one face, electrical connection balls for the external electrical connection of the electronic module. The PCB circuit comprises a hermetically protective electrically insulating inorganic inner layer, and the module comprises six faces with an electrically insulating or conductive inorganic hermetic protection layer on the five faces other than that formed by the PCB circuit.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: November 19, 2019
    Assignee: PACKAGING SIP
    Inventors: Christian Val, Alexandre Val