Patents Assigned to Pan Pacific Semiconductor Co., Ltd.
  • Patent number: 6262479
    Abstract: A semiconductor packaging structure for packaging a semiconductor element comprises: a flat substrate having a chip seat and having a plurality of outer lead wires for electrically connecting the packaging element and the liner. A wall is formed by molding compound and is installed at periphery of the substrate in order to prevent the problem of mold flush in packaging. Bonding wires are connected on the element for electrically connecting the packaging element with outer circuits. The liner extending inwards and outwards than the wall with a predetermined distance to prevent that a mold flush problem will induce in the wall. Therefore, in the present invention, a wall is formed by molding compound for reducing cost and increasing the flexibility in utility.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: July 17, 2001
    Assignee: Pan Pacific Semiconductor Co., Ltd.
    Inventor: Li-Kun Chou
  • Patent number: 6060340
    Abstract: Disclosed is a packaging method of semiconductor device comprising the following step, preparing a PCB or BGA substrate with array-typed dam formed thereupon; placing a plurality of semiconductor devices into the array-typed dam, and attaching each semiconductor devices onto the dam grid; wire-bonding the semiconductor devices; performing lid-covering or resin-sealing process. The present invention forms the dam structure necessary for the package by an off-line process, and then attaches the dam structure on the substrate. Therefore, the problems of damage of PCB or substrate and short circuit due to the high-temperature and high-pressure pressing process can be prevented, moreover, the yield and the reliability can be enhanced.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: May 9, 2000
    Assignee: Pan Pacific Semiconductor Co., Ltd.
    Inventor: Li-Kun Chou
  • Patent number: 5923958
    Abstract: A method for semiconductor chip packaging comprises the following processes: preparing an array-typed base plane by pressing a plane-shaped material, wherein said array-typed base plane comprises a plurality of single-united base surrounded and defined by latticed dams; mounting a already-cut die to each said base unit on said array-typed base plane, and adhering said die to said base unit; wire-bonding said mounted die; applying adhesive paste to top surface of each said dam, and covering the resultant structure with a transparent lid to ensure the hermeticity of the package; cutting said array-typed base plane to a plurality of single-united base. By above-mentioned process, the manufacturing cost can be reduced and the yield can also be enhanced.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: July 13, 1999
    Assignee: Pan Pacific Semiconductor Co., Ltd.
    Inventor: Li-Kun Chou