Patents Assigned to PARADE TECHNOLOGIES, INC.
  • Patent number: 8923375
    Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, ?. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various ? values.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 30, 2014
    Assignee: Parade Technologies, Inc.
    Inventors: Ming Qu, Yuanping Chen, Yuntao Zhu, Quan Yu, Kochung Lee
  • Publication number: 20140003480
    Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, ?. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various ? values.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: PARADE TECHNOLOGIES, INC.
    Inventors: Ming Qu, Yuanping Chen, Yuntao Zhu, Quan Yu, Kochung Lee