Abstract: A method and a digital circuit for synthesizing an input signal to produce an output signal are provided. The circuit includes a delay unit with a delay input and a delay output, a switch, and a controller. The selectively switch routes the input signal to the delay input whereafter the switch routes the delay output to the delay input. The controller controls the delay unit in response to the input signal and the output signal. A counter is provided to count a predetermined number of times the delay output is routed to the delay input whereafter the input signal is routed to the delay input to trigger the delay input. The digital circuit synthesizes the input signal to define a Delay-Locked loop (DLL) in which the delay unit is a voltage controlled delay line (VCDL). The invention extends to a computer program product executing the method and to an embedded circuit including the digital circuit.

Abstract: A method is described that level shifts a differential signal to produce a first signal and level shifts the logical inverse of the differential signal to produce a second signal that is the logical inverse of the first signal. The method then inverts the first signal and inverts the second signal. The method then inverts the first signal and the inverted second signal together and inverts the second signal and the inverted first signal together.

Abstract: An apparatus that has a feedback circuit that couples a wireless receive channel to a frequency synthesizer. A method that reduces an offset in a baseband signal by changing a downconversion frequency in response to the offset.

Abstract: An apparatus is described comprising a current source and a pair of transistors coupled to the current source. A pair of variable loads are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads are coupled to a high gain input and a low gain input. Another apparatus is described comprising an oscillator having a high gain input and a low gain input. The oscillator comprises a series of inverters where each inverter output is coupled to the next inverter input in the series. At least one of the inverters comprises a current source and a pair of transistors coupled to the current source.

Abstract: An apparatus is described comprising a noise source coupled to an input of a gain stage. The apparatus also includes a noise shaping stage that forms a shaped noise signal by reducing 1/f noise introduced by the gain stage. The noise shaping stage has an input coupled to an output of the gain stage. The apparatus also has a decision circuit that decides whether the shaped noise signal, or a signal derived from the shaped noise signal corresponds to a 1 or a 0. A method is described that amplifies a first noise signal to produce a second noise signal. A shaped noise signal is formed by reducing 1/f noise introduced to the second noise signal by the amplifying. A random sequence is generated by comparing, against a reference, the shaped noise signal or a signal derived from the shaped noise signal.

Abstract: A bubble suppression apparatus is disclosed comprising: a first set of AND gates, wherein each AND gate within the first set has an input configured to receive a binary thermometer code value and one or more adjacent binary thermometer code values; and a second set of AND gates, wherein each AND gate within the second set has an input coupled to two or more outputs of the first set of AND gates.