Patents Assigned to Peregrine Semiconductor Corporation
  • Multi-state attenuator
    Patent number: 9531359
    Abstract: Multi-state radio frequency (RF) attenuator configurations that include bridged-T type, pi-type, and T-type structures each having a programmable throughput section and a coupled programmable shunt section. The throughput sections and shunt sections may be configured in various combinations of parallel and serial fixed or selectable resistance elements such that multiple resistance states and impedance matching states can be programmatically selected, and may include stacked switch elements to withstand applied voltages to a specified design level.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: December 27, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Ravindranath Shrivastava
  • ESD protection system, apparatus, and method with adjustable trigger voltage decoupled from DC breakdown voltage
    Patent number: 9509136
    Abstract: Systems, methods, and apparatus for ESD protection with adjustable trigger voltage decoupled from DC breakdown voltage for semiconductor devices including field effect transistors (FETs), and particularly to metal-oxide-semiconductors (MOSFETs) fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates are described. The apparatus and method are configured to change reverse biased drain junctions which in turn can control the DC breakdown voltage and the trigger voltage.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: November 29, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Vadim Kushner, Erica Poole
  • Amplifiers and related biasing methods and devices
    Patent number: 9509263
    Abstract: Biasing methods and devices for amplifiers are described. The described methods generate bias voltages proportional to the amplifier output voltage to control stress voltages across transistors used within the amplifier.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 29, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Fleming Lam
  • Integrated circuit with internal supply override
    Patent number: 9507394
    Abstract: A monolithically integrated circuit with one or more supply overrides without need of an override control pin to the IC is presented. The internal circuitry to control such an override is presented and various override conditions are also presented.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: November 29, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Delay line system and switching apparatus with embedded attenuators
    Patent number: 9503075
    Abstract: A monolithically integrated switch configured to operate at an input signal frequency ranging from 0 Hz to 80 GHz. The switch has an input port and two output ports. A first conduction path is provided from the input port to the first output port. A second conduction path is provided from the input port to the second output port. In addition, a first shunting path is provided between the first output port and a reference and a second shunting path is provided between the second output and the reference. In a first mode, the first conduction path and the second shunting path have a low impedance. The second conduction path and the first shunting path have a high impedance. In a second mode, the first conduction path and the second shunting path have a high impedance. The second conduction path and the first shunting path have a low impedance.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: November 22, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Raul Inocencio Alidio, Peter Bacon
  • Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
    Patent number: 9496849
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: November 15, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Capacitance discharge limiter
    Patent number: 9490647
    Abstract: A capacitance discharge limiter in which a DC transition protection circuit is provided in a circuit that includes a discharge circuit (which may be a power limiter) between a source and a receiver, with a capacitor situated between the source and the discharge circuit. The DC transition protection circuit is coupled to a reference voltage and to the control voltage input of the discharge circuit, and also between the capacitor and the discharge circuit at a node. The DC transition protection circuit detects the existence of an excess DC or low frequency (typically less than about 1 MHz) voltage potential at the node caused by charge on the capacitor, and regulates the control voltage so as to enable the discharge circuit to discharge the capacitor to protect the receiver.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: November 8, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Hojung Ju, Jianhua Lu
  • Level shifter
    Patent number: 9484897
    Abstract: Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: November 1, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Merlin Green, Mark L. Burgener, James W. Swonger, Buddhika Abesingha, Ronald Eugene Reedy
  • Reduced generation of second harmonics of FETs
    Patent number: 9461037
    Abstract: A structure and method for reducing second-order harmonic distortion in FET devices used in applications that are sensitive to such distortion, such as switching RF signals. The asymmetry of the drain-to-body capacitance Cdb and source-to-body capacitance Csb of a FET device are equalized by adding offsetting capacitance or a compensating voltage source.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: October 4, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Alper Genc
  • Scalable periphery for digital power control
    Patent number: 9455670
    Abstract: A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of PMOS transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source. The plurality of PMOS transistors that is operatively coupled to the voltage source can operate as a controlled current source. Current flow from the voltage source can be controlled by a logic circuit, which sends a logic signal to enable or disable each individual PMOS transistor of the plurality of PMOS transistors connected in parallel. As more PMOS transistors are enabled, the current flow through the scalable periphery digital power control arrangement to the amplifier can increase.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: September 27, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: David Kovac
  • Digital step attenuator with reduced relative phase error
    Patent number: 9444432
    Abstract: An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: September 13, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Ravindranath Shrivastava, Kristian Madsen
  • Low phase noise frequency divider
    Patent number: 9444465
    Abstract: A low phase noise frequency divider suitable for use in phase locked loops (PLL) and frequency synthesizers, particular in a fractional-N PLL system having an N frequency divider with a main (M) counter and an auxiliary (A) counter. In some user selectable cases, the count value CM for the M counter is fixed and only the count value CA for the A counter is varied. Having a fixed CM value results in lower phase noise in most cases. For cases where it is not possible to vary CM, then CM is allowed to vary in a conventional manner to retain a full range of functionality.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: September 13, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Gary Chunshien Wu
  • Integrated tunable filter architecture
    Patent number: 9438196
    Abstract: An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: September 6, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: William R. Smith, Jaroslaw Adamski, Dan William Nobbe, Edward Nicholas Comfoltey, Jingbo Wang
  • Devices and methods for increasing reliability of scalable periphery amplifiers
    Patent number: 9438185
    Abstract: Devices and methods for improving reliability of sealable periphery amplifiers is described. Amplifier segments of the sealable periphery architecture can be rotated to distribute wear. Further, extra amplifier segments can be implemented on amplifier dies to extend the overall lifetime of amplifiers.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: September 6, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Chris Olson
  • Low-noise high efficiency bias generation circuits and method
    Patent number: 9429969
    Abstract: Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: August 30, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tae Youn Kim, Robert Mark Englekirk
  • System and method for tuning an RF circuit
    Patent number: 9425762
    Abstract: A tuning system connected to a tunable RF circuit is described. The tuning system obtains an output of a sensing circuit and processes the output in the control circuit in order to tune one or more passive components in the tunable RF circuit. A related method is also described.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: August 23, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: David Kovac, Dan William Nobbe
  • Hot carrier injection compensation
    Patent number: 9419565
    Abstract: Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: August 16, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, Chris Olson, David Kovac
  • Amplifier dynamic bias adjustment for envelope tracking
    Patent number: 9413298
    Abstract: An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 9, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, Jeffrey A. Dykstra, Chris Olson, James S. Cable
  • Differential charge pump
    Patent number: 9413362
    Abstract: A DC-to-DC voltage converter comprising a differential charge pump that utilizes a differential clocking scheme to reduce output electrical noise by partial cancellation of charge pump glitches (voltage transients), and a corresponding method of operating a differential charge pump. The differential charge pump can be characterized as having at least two charge pump sections that initiate charge pumping in opposite phases of a clock signal to transfer (pump) charge to storage capacitors. The differential charge pump is particularly well suited for implementation in integrated circuit chips requiring negative and/or positive voltages, and multiples of such voltages, based on a single input voltage.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: August 9, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Circuit and method for improving ESD tolerance and switching speed
    Patent number: 9406695
    Abstract: Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on semiconductor-on-insulator and silicon-on-sapphire substrates. Embodiments provide an improved FET structure having an accumulated charge sink (ACS) circuit, fast switching times, and improved ESD tolerance.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 2, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Eric S. Shapiro, Matt Allison