Abstract: An apparatus and a method for protecting boot block code while allowing updating to BIOS code during a flash BIOS operation. The boot block code is stored in a boot block or boot region of a flash part, and then a copy of the boot block code is written into another region of the flash part. The image of the boot block code in the another region is compared with the boot block code in the boot block, and if there is a match, the boot block region is unprotected, thereby allowing an update of code in the boot block. The boot block code of the flashed-in BIOS image in the boot block region is compared with the copy of the boot block code in the another region, and if there is a match, the code in the boot block region is protected. If there is not a match or if a power failure occurs, the system is booted up using the boot block code in the another region.

Abstract: A method and computer system including a bootable storage media, preferably a CD-ROM, having a single bootable disk image that allows multiple emulations. A hard disk boot image including an MBR is provided at the beginning of the bootable disk image. A floppy DBR is provided at a predetermined sector boundary in the hard disk image so that the computer system can use either the hard disk or the floppy disk emulation at boot time. A computer article of manufacture embodying a single bootable disk image that allows both a hard disk or a floppy disk emulation is also provided.

Abstract: The present invention is an apparatus and method for specifying operation of a boot device in a processor-based system. The apparatus comprises a memory for storing instruction sequences by which the processor-based system is processed and a processor for executing the stored instruction sequences. The stored instruction sequences cause the processor to: (a) determine if a boot process should proceed from a currently specified drive; (b) if not, specify a drive from which the boot process will proceed; and (c) initiate the boot process.

Abstract: An apparatus and method for accessing a writeable storage in a processor-based system. The apparatus comprises at least one writeable storage element and memory for storing instruction sequences by which the processor-based system is processed, that has a writeable storage location. A processor is coupled to the writeable storage element and executes the stored instruction sequences. The stored instruction sequences include process steps to cause the processor to: (a) detect an access to the writeable storage location; (b) transfer the access to the writeable storage location to an access to the writeable storage element; (c) process an instruction sequence corresponding to the access to the writeable storage element.

Abstract: A display process for displaying predetermined image data in a computer that includes a processor, a fast memory, and a video system having a video memory, comprising the steps of: during a computer execution period, writing contents from a block of the fast memory to a first memory, the fast memory having an access time which is less than an access time for the video memory; writing predetermined image data into the block of the fast memory; processing the predetermined image data from the fast memory; and writing the processed predetermined image data to the video memory.

Abstract: A method and article of manufacture for the automatic generation of Advanced Configuration and Power Management Interface (“ACPI”) Source Language (“ASL”) code in a Basic Input-Output System (“BIOS”) of a computer system having an ACPI compliant BIOS. The method scans all device node structures in the BIOS to find the device node structures corresponding to static and MCD devices. ASL code is generated corresponding to the device node structure by extracting the PnP Id of the devices and generating the required control methods.

Abstract: A method and article of manufacture for the run-time modification of Advanced Configuration and Power Management Interface ("ACPI") Machine Language ("AML") code in a Basic Input-Output System ("BIOS") of a computer system having an ACPI compliant BIOS. One aspect includes scanning all the AML code in the BIOS and finding all objects that meet a specified criterion, and modifying the AML that corresponds to the objects found based on the specified criterion. Another aspect includes scanning all the system code in a non-volatile memory of the computer system to determine device options modified by a user's preferences, and modifying the AML to reflect the user's preferences.

Abstract: A method and system for dynamic creation of APIC tables under the ACPI specification using existing APIC tables under the MP specification in a multi-processor computer. The method of the present invention provides for the dynamic creation of APIC entries in a computer memory, and includes the steps of: scanning the memory for an MP APIC header, reading MP APIC entries from a location in the memory indicated by the MP APIC header, building ACPI APIC entries in the memory from at least a portion of the MP APIC entries read, and updating an ACPI APIC header in the memory after the ACPI APIC entries have been built.

Abstract: In accordance with one aspect of the current invention, the system comprises a memory for storing instruction sequences by which the processor-based system is processed, where the memory includes a physical memory and a virtual memory. The system also comprises a processor for executing the stored instruction sequences. The stored instruction sequences include process acts to cause the processor to: map a plurality of predetermined instruction sequences from the physical memory to the virtual memory, determine an offset to one of the plurality of predetermined instruction sequences in the virtual memory, receive an instruction to execute the one of the plurality of predetermined instruction sequences, transfer control to the one of the plurality of predetermined instruction sequences, and process the one of the plurality of predetermined instruction sequences from the virtual memory.

Abstract: To improve the speed of transition to the zero-volt suspend state, system context is saved from volatile random access memory to non-volatile memory, such as a hard disk, using a compression algorithm which speeds the transfer of data to non-volatile memory by recognizing data pages having bytes of a single value. The system context in extended memory of RAM consists of a number of system context memory blocks, and between these memory blocks are memory holes containing information which does not require storage. Initially, the entirety of data in a buffer region of RAM is stored directly to disk. Then, successive pages from each system context memory block are transferred to the buffer, where the page size corresponds to the memory management unit page size. When testing locates a region of heterogeneous entries, then a heterogeneous-data flag, the length of the heterogeneous region, and the heterogeneous data region are transferred to the buffer.

Abstract: A method for managing power in an electronic system having a plurality of input/output devices, each of the input/output devices having a full power-on state and at least one power reduction state and each being controlled by an associated device driver, the method comprising the steps of: initializing a power management logic separate from the device drivers to receive at least one time-out value for each of the device drivers to be subject to power management; assigning a different timer in the power management logic to a different one of the device drivers to be subject to power management, the timers being disposed external of the device drivers; initializing each of a plurality of the assigned timers to individual predetermined value set in accordance with the at least one time out value of the assigned device driver for that timer; changing the individual predetermined value held in each of the timers at a predetermined interval; monitoring a plurality of the timers and determining when the predetermine

Abstract: Data representing bitmapped graphics and/or text characters is stored in a video buffer or memory of a computer. A window is designated that includes contiguous rows and columns of data to be scrolled. The data in the window is vertically scrolled by columns. One column can be scrolled at a time, or two or more adjacent or alternating columns can be scrolled at a time. The column scrolling method is faster than scrolling by rows when the number of rows in the window is small and/or the number of rows to scroll is high. Program instructions for implementing the scrolling are preferably stored in a Basic Input-Output System (BIOS) Read-Only Memory (ROM) chip to provide a built-in, backward compatible low resolution display capability, e.g. a Color Graphics Adapter (CGA) text display, for a newer computer or other data processing device.

Abstract: A method and apparatus for enabling the use of two or more pointing devices with a computer, where the pointing devices generate data packets of different sizes. The maximum size of the data packets generated by the pointing devices is determined. Any data packets received from the pointing devices which are smaller than the maximum size have additional bytes added to increase the size of the data packet to the maximum size. Thus, the computer receives the same size data packets from all of the pointing devices, facilitating the use of multiple pointing devices.

Abstract: A Basic Input-Output System (BIOS) Read-Only Memory (ROM) for a computer system includes a color expansion table, and a storage for storing a computer program for generating an output character represented by bitmapped output scan lines from a corresponding input character represented by bitmapped input scan lines which have a smaller number of bits than the output scan lines. The input scan lines are each preferably one byte long, with one pixel being represented by one bit. The output scan lines are each preferably one word long, with each pixel being represented by two bits to provide four selectable colors or shades of grey. The computer program includes instructions for accessing the expansion table with the input scan lines to obtain corresponding output scan lines. The expansion table includes entries which are addressable by a nibble of an input scan line and contain a corresponding byte of an output scan line, and separate sections for the four colors.

Abstract: A Basic Input-Output System (BIOS) includes a management and driver module adapted to accomplish editing functions for the BIOS. Plug-in modules are added to the BIOS by submitting the plug-ins to the driver module, which determines compatibility and available space for adding, and acts accordingly, adding a candidate module to the BIOS if space is available and the plug-in module is determined to be compatible with the BIOS and the driver module. Plug-ins can also be removed by action of the driver module, which also performs management functions in identifying and initializing resident plug-in modules.

Abstract: A system for creating a communication interface between a first finite state machine, operating in accordance with a write side clock in a write side clock domain, the first finite state machine operating to generate a Request signal for a transaction and for requesting the transfer of information associated with the Request signal, and a second finite state machine, operating in accordance with a read side clock in a read side clock domain at a different frequency than the write side clock, comprising: a register file; a first interface to the first finite state machine; a second interface to the second finite state machine; and logic for loading in accordance with the write side clock, a communication queue of the information into the register file in accordance with the Request signals from the first finite state machine, for reading by the second finite state machine via the second interface in accordance with the read side clock.

Abstract: The present invention is an apparatus and method for executing instructions in a system management mode in a processor-based system. The apparatus comprises a memory for storing instruction sequences by which the processor-based system is processed where the memory includes a system management random access memory (SMRAM). The apparatus also comprises a processor having a system address space, that executes the stored instruction sequences. The stored instruction sequences include process steps to cause the processor to: (a) configure the processor to operate in a protected mode while in a system management mode, the processor operating at address greater than one megabyte; (b) invoke a paging feature of the processor; (c) configure the processor to operate in a virtual mode; and (d) process the instruction sequences; wherein the process steps occur upon the receipt of an instruction to process a system management request.

Abstract: A single controller handles keyboard functions and ACPI configuration and power management functions, while providing priority to keyboard functions so that there is no end user-perceptible compromise of keyboard functionality. When an interrupt is received by the microcontroller, it is determined whether the interrupt is an embedded controller interrupt received at the embedded controller host interface or a keyboard interrupt received at the keyboard host interface. If the interrupt is a keyboard interrupt, the keyboard function is handled in a standard fashion. If the interrupt is an embedded controller interrupt for an ACPI configuration or power management function, a burst timer is started and the command is handled by a command dispatcher. If the embedded controller is in burst mode, multiple commands may be received during a burst period.

Abstract: A display system receives a data stream having successive image frame data in frame regions and Internet Universal Resource Locator (URL) data and association data in data regions between frame regions, and displays on a display monitor successive frames derived from the image frame data. The association data associates one or more image entities in successive frames with one or more URLs, and a viewer, by selecting an associated image entity in the display, causes the system to access the Internet, to connect to a source on the Internet associated with the URL, to download a WEB page from the source, and to display the WEB page in the display. The viewer may interact with the displayed WEB page to access further related information. Entities may be enhanced in the display to indicate association with a hidden URL.

Abstract: A chipset (platform)-independent method and apparatus for compressing and decompressing a system ROM of a computer (e.g., BIOS, setup program, and one or more option ROMs) are disclosed. The setup program, option ROM, and part of the BIOS are compressed using a lossless compression algorithm. A non-compressible portion of the BIOS includes a decompression algorithm and a shadow RAM block table of chipset-specific registers and bit patterns to write-enable and read-enable shadow RAM (RAM that is mapped to the ROM address space). The compressed data is stored in a compressed data block format with the associated location in memory to decompress the compressed data. Thus, the data can be decompressed anywhere in memory of a target computer. For example, the BIOS is decompressed to shadow RAM and the setup program is decompressed to conventional memory. During the BIOS Power-On Self-Test (POST) process, the compressed system ROM is copied to conventional memory, and the decompression program is executed.