Patents Assigned to Plato Labs, Inc.
  • Analog adaptive line equalizer
    Patent number: 6169764
    Abstract: A low cost and low power adaptive cable equalizer that is particularly suitable for fast Ethernet data communication is disclosed. According to various embodiments of the present invention, first and second order adaptive equalizers are implemented using CMOS continuous-time analog signal processing, with variable resistors, linear capacitors and high-speed operational amplifiers.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: January 2, 2001
    Assignee: Plato Labs, Inc.
    Inventor: Joseph N. Babanezhad
  • Digitally controlled tuner circuit
    Patent number: 6069505
    Abstract: A digitally controlled tuner circuit for continuous-time filters. Active RC integrators include digitally programmable feedback capacitors to allow for digital fine tuning of their time constant. The PLL-based tuner circuit includes a sine-wave oscillator made up of the digitally-controlled active RC integrators.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: May 30, 2000
    Assignee: Plato Labs, Inc.
    Inventor: Joseph N. Babanezhad
  • Low voltage transmission line driver
    Patent number: 6028479
    Abstract: A high-speed low-voltage line-driver circuit implemented using various embodiments of high speed current-feedback opamps is disclosed. The line driver of the present invention uses a fully differential architecture whereby common-mode disturbances, such as noise due to substrate or power supply, are cancelled. The driver also uses a current-feedback approach to achieve larger bandwidth. In a specific embodiment, the current-feedback opamp used in the line driver of the present invention uses class A/B structure for both input and output stages.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: February 22, 2000
    Assignee: Plato Labs, Inc.
    Inventor: Joseph N. Babanezhad
  • PLL-based differential tuner circuit
    Patent number: 5936445
    Abstract: Various circuit techniques to implement continuous-time filters with improved performance are disclosed. The present invention uses RMC type integrators that exhibit lower harmonic distortion. In one embodiment, a novel high-gain two-pole operational amplifier is used along with RMC architecture to achieve lower harmonic distortion. In another embodiment, the present invention uses dummy polysilicon resistors to accurately compensate for the distributed parasitics of the polysilicon resistors used in RMC integrator. In yet another embodiment, the present invention provides an on-chip tuner with a differential architecture for better noise immunity.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: August 10, 1999
    Assignee: Plato Labs, Inc.
    Inventors: Joseph N. Babanezhad, Emad Afifi
  • Wide band-width operational amplifier
    Patent number: 5880634
    Abstract: Various circuit techniques to implement continuous-time filters with improved performance are disclosed. The present invention uses RMC type integrators that exhibit lower harmonic distortion. In one embodiment, a novel high-gain two-pole operational amplifier is used along with RMC architecture to achieve lower harmonic distortion. In another embodiment, the present invention uses dummy polysilicon resistors to accurately compensate for the distributed parasitics of the polysilicon resistors used in RMC integrator. In yet another embodiment, the present invention provides an on-chip tuner with a differential architecture for better noise immunity.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: March 9, 1999
    Assignee: Plato Labs, Inc.
    Inventor: Joseph N. Babanezhad
  • Compensation technique for parasitic capacitance
    Patent number: 5744385
    Abstract: Various circuit techniques to implement continuous-time filters with improved performance are disclosed. The present invention uses RMC type integrators that exhibit lower harmonic distortion. In one embodiment, a novel high-gain two-pole operational amplifier is used along with RMC architecture to achieve lower harmonic distortion. In another embodiment, the present invention uses dummy polysilicon resistors to accurately compensate for the distributed parasitics of the polysilicon resistors used in RMC integrator. In yet another embodiment, the present invention provides an on-chip tuner with a differential architecture for better noise immunity.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: April 28, 1998
    Assignee: Plato Labs, Inc.
    Inventor: Pirooz Hojabri