Abstract: Described are various embodiments of systems, methods and devices for transmitting, over a digital network, a digital image data object defined by a plurality of image pixels, wherein embodiments comprise: a digital image compressor operable to compress the digital image data object by independently compressing distinct pixel groups defined amongst the plurality of image pixels into independently compressed pixel groups to be transmitted over the digital network, in which, for each of said compressed pixel groups, a comparison value indicative of a similarity between given pixel data of a given group pixel and reference pixel data of a corresponding reference pixel is computed to at least partially replace said given pixel data; and a digital image decompressor coupled thereto operable to receive each of said independently compressed pixel groups for independent decompression.
Abstract: A method and system for interconnecting peripherals, processor nodes, and hardware devices to a data network to produce a network bus providing OS functionality for managing hardware devices connected to the network bus involves defining a network bus driver at each of the processor nodes that couples hardware device drivers to a network hardware abstraction layer of the processor node. The network bus can be constructed to account for the hot-swappable nature of the hardware devices using a device monitoring function, and plug and play functionality for adding and, removing device driver instances. The network bus can be used to provide a distributed processing system by defining a shared memory space at each processor node. Distributed memory pages are provided with bus-network-wide unique memory addresses, and a distributed memory manager is added to ensure consistency of the distributed memory pages, and to provide a library of functions for user mode applications.
Abstract: This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video source without an operating system. The method relates to operation of a microprocessor which is suitably arranged to carry out the steps of the method. The method includes details of operation of the specialized microprocessor.
Type:
Grant
Filed:
February 27, 2004
Date of Patent:
June 3, 2008
Assignee:
Pleora Technologies Inc.
Inventors:
Eric Boisvert, Alain Rivard, George Chamberlain
Abstract: A method and system for interconnecting peripherals, processor nodes, and hardware devices to a data network to produce a network bus providing OS functionality for managing hardware devices connected to the network bus involves defining a network bus driver at each of the processor nodes that couples hardware device drivers to a network hardware abstraction layer of the processor node. The network bus can be constructed to account for the hot-swappable nature of the hardware devices using a device monitoring function, and plug and play functionality for adding and, removing device driver instances. The network bus can be used to provide a distributed processing system by defining a shared memory space at each processor node. Distributed memory pages are provided with bus-network-wide unique memory addresses, and a distributed memory manager is added to ensure consistency of the distributed memory pages, and to provide a library of functions for user mode applications.