Abstract: A system and method for dynamically protecting a vulnerable device from an ESD event includes an ESD event sensor and a breakdown voltage adjustment circuit. The ESD event sensor detects an ESD event and provides a signal to the breakdown voltage adjustment circuit indicating that an ESD event has occurred. The breakdown voltage adjustment circuit receives the signal from the ESD event sensor and adjusts the breakdown voltage of the vulnerable device during the ESD event.

Abstract: A method of forming a semiconductor device on a substrate. The method includes forming a first epitaxial layer on the substrate. Next, a selected impurity is introduced to a surface of the first epitaxial layer. A second epitaxial layer is then formed on the surface of the first epitaxial layer and over the selected impurity. Finally, the selected impurity is driven through the first epitaxial layer and the second epitaxial layer to form the desired doped regions.

Abstract: A method to create a layout of a semiconductor device for the purpose of fabricating the semiconductor device involves first providing a plurality of partial-area layout cells and then generating the layout of the semiconductor device by placing the plurality of the partial-area layout cells together. The layout can be conveniently expanded to a desirable size by replicating or repeating certain repeatable cells.

Abstract: The present invention provides an over-voltage protection circuit using a Zener diode and transistor. By disposing at least one junction region of the Zener diode outside of the base region of the transistor, a tight (i.e., with small variation) and suitably high reverse breakdown voltage is achieved.

Abstract: An integrated circuit having very low parasitic current gain includes a guard ring that is used to completely surround a device, such as a power device, that induces parasitic current. The guard ring is formed in a semiconductor body layer such as an epitaxial layer and has a central guard ring of the same type conductivity as that of the body layer and additional flanking rings of the opposite type conductivity. An unbiased configuration of the guard ring based on the above structure is particularly effective in reducing the parasitic gain. The effectiveness of the guard ring, such as the high current performance, is further improved by reducing the resistance between neighboring rings using various methods.