Abstract: A method for manufacturing a capacitor bottom electrode of a dynamic random access memory is provided. The method comprises providing a substrate having a memory cell region and forming a polysilicon template layer on the memory cell region of the substrate. A supporting layer is formed on the polysilicon template layer and plural openings penetrating through the supporting layer and the polysilicon template layer are formed and a liner layer is formed on at least a portion of the polysilicon template layer exposed by the openings. A conductive layer substantially conformal to the substrate is formed on the substrate. A portion of the conductive layer on the supporting layer is removed so as to form plural capacitor bottom electrodes. Using the polysilicon template layer, the openings with relatively better profiles are formed and the dimension of the device can be decreased.

Abstract: A mask for dual tone development including a opening pattern region and a partial transparent pattern is provided. The opening pattern region includes a plurality of transparent patterns and a plurality of opaque patterns, and a plurality of opening patterns is defined in a photoresist for dual tone development by the transparent patterns and the opaque patterns. The partial transparent pattern surrounds the opening pattern region.

Abstract: A manufacturing method of a vertical channel transistor array is provided. The method includes following steps. A plurality of embedded word lines are formed at bottoms of trenches, and each of the embedded word lines is located at a first side wall of one of the trenches and connected to first sides of the semiconductor pillars in the same row. Each of the embedded word lines is not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides. Only one embedded word line is correspondingly connected to the semiconductor pillars arranged in one row. An isolation structure is formed between a second side wall of each of the trenches and each of the embedded word lines. The first side wall is opposite to the second side wall.

Abstract: A non-volatile semiconductor device includes: memory strings formed by series connection of memory cells respectively connected to word lines, wherein each memory string is connected between a bit line and a source line via first and second select gate transistors; and a control circuit controlling the first and second select gate transistors, such that when voltage of the word line is raised to a predetermined value for data readout from the memory cell, a first status where the first select gate transistor is turned on and the second select gate transistor is turned off and second status where the first select gate transistor is turned off and the second select gate transistor is turned on are generated alternately.

Abstract: A method of fabricating a semiconductor component that including the following steps is provided. A plurality of stacked structures is formed on a substrate. A first dielectric layer is formed to cover the stacked structures, wherein the first dielectric layer has a plurality of overhangs, the overhangs wrap top portions of the stacked structures. A dry conformable etching process is performed to conformably remove the first dielectric layer until a portion of the first dielectric layer located outside of the overhangs is removed. A second dielectric layer is formed on the stacked structures, wherein the second dielectric layer connects the adjacent overhangs to form an air gap between the stacked structures.

Abstract: A vertical channel transistor array includes a plurality of embedded bit lines, a plurality of bit line contacts, a plurality of embedded word lines, and a current leakage isolation structure. An active area of a vertical channel transistor is defined by the semiconductor pillars. The embedded bit lines are disposed in parallel in a semiconductor substrate and extended in a column direction. Each of the bit line contacts is respectively disposed at a side of one of the embedded bit lines. The embedded word lines are disposed in parallel above the embedded bit lines and extended in a row direction. Besides, the embedded word lines and the semiconductor pillars in the same row are connected but spaced by a gate dielectric layer. The current leakage isolation structure is disposed at ends of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.

Abstract: A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction.

Abstract: A non-volatile semiconductor memory device, comprising: a non-volatile memory array, storing multi-values by setting a plurality of different threshold voltages for each memory cell, and a control circuit, controlling a write-in operation to the memory cell array. When data have been written into the memory cell, the control circuit selects an adjacent word line, uses an erasing level to perform write-in which is weaker than the data write-in, and verifies soft programming of the amount of one page, such that a narrow-banded erasing level distribution is realized in an adjacent memory cell.

Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

Abstract: A method of fabricating a non-volatile memory is provided. A tunneling dielectric layer and a first patterned conductive layer are sequentially formed on a substrate. A patterned inter-gate dielectric layer and a second patterned conductive layer are stacked on a first surface of the first patterned conductive layer, and a second surface of the first patterned conductive layer is exposed. The second surface is adjacent to the first surface. The substrate is covered by a passivation layer, and a first sidewall of the first patterned conductive layer is exposed. A recess is formed on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner. A portion of the passivation layer on the second surface is removed, such that the sharp corner of the first patterned conductive layer is exposed.

Abstract: A method for forming a contact window includes: a step of providing a substrate; a step of forming a patterned amorphous carbon layer or spin-on coating layer, in which a surface of the substrate is exposed at two sides of the amorphous carbon layer or spin-on coating layer; a step of forming an interlayer dielectric layer on the substrate; a step of removing a portion of the interlayer dielectric layer until the patterned amorphous carbon layer or spin-on coating layer is exposed; a step of removing the patterned amorphous carbon layer or spin-on coating layer to form an opening; and a step of filling the opening with a conductive material to form the contact window.

Abstract: A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer.

Abstract: A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.

Abstract: In a non-volatile semiconductor memory device outputting a data value determined according to a majority rule by reading-out data from each memory cell for an odd number of times, an odd number of latch circuits, each of which comprises a capacitor for selectively holding a voltage of each of the data read-out from the memory cell for the odd number of times in sequence, is provided. The capacitor of each latch circuit is connected in parallel after the capacitor of each latch circuit selectively holds the voltage of each of the data read-out from the memory cell for the odd number of times in sequence, and the data value is determined by the majority rule based on a composite voltage of the capacitor of each latch circuit connected in parallel.

Abstract: A non-volatile semiconductor device includes: memory strings formed by series connection of memory cells respectively connected to word lines, wherein each memory string is connected between a bit line and a source line via first and second select gate transistors; and a control circuit controlling the first and second select gate transistors, such that when voltage of the word line is raised to a predetermined value for data readout from the memory cell, a first status where the first select gate transistor is turned on and the second select gate transistor is turned off and second status where the first select gate transistor is turned off and the second select gate transistor is turned on are generated alternately.

Abstract: A method for forming a contact window includes: a step of providing a substrate; a step of forming a patterned amorphous carbon layer or spin-on coating layer, in which a surface of the substrate is exposed at two sides of the amorphous carbon layer or spin-on coating layer; a step of forming an interlayer dielectric layer on the substrate; a step of removing a portion of the interlayer dielectric layer until the patterned amorphous carbon layer or spin-on coating layer is exposed; a step of removing the patterned amorphous carbon layer or spin-on coating layer to form an opening; and a step of filling the opening with a conductive material to form the contact window.

Abstract: TASK: to provide an internal voltage trimming circuit having a simple configuration and operated by a consumption current smaller than that using a comparator. MEANS FOR SOLVING THE PROBLEM: An internal voltage trimming circuit comprises a trimming controller using a change in a counting value of a clock according to a current flowing through a transistor of a power supply current source for a clock generator to trim an internal voltage generated by an internal voltage generator. The trimming controller counts a first counting value of the clock when a predetermined reference voltage is applied to a control terminal of the transistor and a second counting value of the clock when the internal voltage is applied to the control terminal of the transistor and controls the internal voltage generated by the internal voltage generator to substantially coincide the second counting value with the first counting value.

Abstract: A method of fabricating a semiconductor component that including the following steps is provided. A plurality of stacked structures is formed on a substrate. A first dielectric layer is formed to cover the stacked structures, wherein the first dielectric layer has a plurality of overhangs, the overhangs wrap top portions of the stacked structures. A dry conformable etching process is performed to conformably remove the first dielectric layer until a portion of the first dielectric layer located outside of the overhangs is removed. A second dielectric layer is formed on the stacked structures, wherein the second dielectric layer is connected to connects the adjacent overhangs to form an air gap between the stacked structures.

Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

Abstract: A level shift circuit, for outputting a data output signal with a second level via an output inverter after a data input signal with a first level is stored in a latch, includes a level set circuit, when the output data signal outputs with a low level, setting the output data signal to a low level in response to a change of the input data signal. The level set circuit is connected to an output terminal of the output inverter, and has an NMOS transistor having a drain electrode and a source electrode coupled to a ground, wherein the NMOS transistor turns on in response to the input data signal with a high level.