Abstract: Measurement apparatus, for generating a first output signal indicative of a measurand, comprises: a first oscillator circuit and a second oscillator circuit, each oscillator circuit being arranged to generate a respective oscillating output signal and comprising at least a respective first component having a property determining a respective output frequency of the respective oscillating output signal; a sensor for sensing said measurand, the sensor comprising said first component of the first oscillator circuit, said property of said first component of the first oscillator circuit being dependent upon said measurand; and circuitry arranged to receive said oscillating output signals and generate said first output signal, said first output signal being indicative of a number of cycles of one of the first and second oscillating output signals in a time period determined by a period of the other of said first and second oscillating output signals.

Abstract: An electronic circuit is described, comprising: a first power rail; a second power rail; and a field effect transistor, FET, the FET comprising: a first terminal coupled directly or indirectly to the first power rail; a second terminal coupled directly or indirectly to the second power rail; a channel of semiconductive material connecting the first terminal to the second terminal; a gate terminal to which a voltage may be applied to control a conductivity of the channel, the channel providing a conduction path from the first terminal to the second terminal; and a gate dielectric arranged to insulate the gate terminal from the channel. The circuit further comprises a layer or other body of dielectric material, the gate dielectric being a first portion of the layer or other body of dielectric material.

Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.

Abstract: There is provided an oscillator, having an input terminal (In) and an output terminal (Out), comprising a first signal delay circuit (104a-d), having a first voltage response characteristic, configured to provide a predetermined first propagation delay; a second signal delay circuit (104e, 108, 110), having a second voltage response characteristic that is inversely correlated to said first voltage response characteristic, operatively coupled with said first signal delay circuit and configured to provide a predetermined second propagation delay, and wherein said predetermined first propagation delay and said predetermined second propagation delay are temporally matched, so as to generate an oscillating output signal (Out) of a predetermined frequency.

Abstract: The invention relates to a thermode for connecting at least two components, comprising a tip having a body portion with at least two contact surface portions connected to and spaced apart from one another by a recess configured to receive a portion of one of the at least two components; and a support portion having at least one supporting surface portion configured to support a further component (being the other of the at least two components, wherein the contact surface portions and the supporting surface portion are configured to receive the at least two components between them and wherein one or both of the contact surface portions and the supporting surface portion are moveable relative to and towards one another to exert heat and/or pressure on the at least two components located between the contact surface portions and the supporting portion.

Abstract: The present invention provides for a RFID tag assembly that is suitable for operation with at least one RFID reader assembly. The RFID tag assembly comprises, inter alia, an antenna member for transmitting and/or receiving an RFID signal, and at least one integrated circuit (IC) for processing the RFID signal and which is configured to communicate, alternatingly and sequentially in time, a first signal transmission and at least one second signal transmission, each defined by a plurality of predetermined signal transmission parameters, to the at least one RFI D reader assembly, utilising time-division multiplexing, wherein the at least one first signal transmission differs from the at least one second signal transmission in at least one of said plurality of predetermined signal transmission parameters.

Abstract: A method, apparatus and system for secure one-way RFID tag identification is provided. The method comprising generating, at an RFID tag, an auxiliary identifier; generating, at an RFID tag, a secure representation based on the auxiliary identifier; transmitting, from the RFID tag and receiving at an RFID reader, one or more representations of the auxiliary identifier and the tag identifier including the secure representation; and verifying the identity of the RFID tag based on the received representations.

Abstract: There is provided a dual-slope analog-to-digital converter (ADC), comprising an input signal terminal, configured to provide an analog signal, and a reference signal terminal, configured to provide a predetermined reference signal. The ADC further comprises an integrator, that is operatively coupled to said input signal terminal and said reference signal terminal via a first switch unit, said first switch unit being configured to selectively connect and disconnect said integrator to and from any one of said input signal terminal and said reference signal terminal.

Abstract: One exemplary aspect relates to a process and apparatus for selectively changing adhesion strength between a flexible substrate and a carrier at specific locations to facilitate shipping and subsequent removal of the flexible substrate from the carrier. The process includes providing a flexible substrate comprising a plurality of integrated circuits thereon providing a carrier for the flexible substrate and adhering the flexible substrate to the carrier by creating an interface between the flexible substrate and the carrier. The process further includes changing the adhesion force between the flexible substrate and the carrier at selected locations by non-uniform treatment of the interface between the flexible substrate and the carrier with an electromagnetic radiation source (e.g. a laser, flashlamp, high powered LED, an infrared radiation source or the like) so as to decrease or increase the adhesion force between a portion of the flexible substrate and the carrier at the selected location.

Abstract: A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

Abstract: An AND gate comprises: a first input; a second input; an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output.

Abstract: A RFID (Radio Frequency Identification) system is provided, comprising at least one tag assembly having at least one tag inductance element that is operatively coupled to an integrated circuit (IC). The RFID system further comprises at least one reader assembly having at least one reader inductance element that is configured to operatively and communicatively couple with the tag assembly, and a resonance assembly having at least one first resonance element that is inductively coupleable to the at least one tag inductance element and/or at least one second resonance element that is inductively coupleable to the at least one reader inductance element, and which is adapted to provide coupled magnetic resonance signal transmission between the reader assembly and the tag assembly.

Abstract: A method, apparatus and system for secure one-way RFID tag identifications provided. The method comprising generating, at an RFID tag, an auxiliary identifier; generating, at an RFID tag, a secure representation based on the auxiliary identifier; transmitting, from the RFID tag and receiving at an RFID reader, one or more representations of the auxiliary identifier and the tag identifier including the secure representation; and verifying the identity of the RFID tag based on the received representations.

Abstract: The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.

Abstract: An RFID tag for capacitively coupled RFID communication with an RFID reader. The RFID tag comprising an integrated circuit (IC), the IC including a first RFID tag electrode arranged to capacitively couple with a first electrode of the RFID reader to form a first capacitor, and a second RFID tag electrode arranged to capacitively couple with a second electrode of the RFID reader to form a second capacitor when the RFID tag is in a first position relative to the RFID reader; power supply circuitry configured to extract power from a first time-varying signal received from the RFID reader via at least one of the first RFID tag electrode and the second RFID tag electrode, and supply the extracted power to circuitry of the RFID tag; and data transmission circuitry configured to receive the extracted power from the power supply circuitry, and transmit data to the RFID reader via at least one of the first RFID tag electrode and the second RFID tag electrode.

Abstract: The present invention relates to a method and apparatus for manufacturing a plurality of electronic circuits, each electronic circuit comprising a respective flexible first portion, comprising a respective group of contact pads (contacts), and a respective flexible integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad, the method comprising: providing (e.g. manufacturing) a flexible first structure comprising the plurality of first portions; providing (e.g.

Abstract: An AND gate comprises: a first input; a second input; an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output.

Abstract: A method of manufacturing a plurality of electronic circuits is disclosed. Each electronic circuit comprises a respective first portion, comprising a respective group of contact pads, and a respective integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad. The method comprises: providing a first structure comprising the plurality of first portions; providing a second structure comprising the plurality of ICs and a common support arranged to support the plurality of ICs; transferring said ICs from the common support onto a first roller having a removable surface portion; and transferring said ICs from the first roller onto the first structure such that each group of terminals is mounted on a respective group of contact pads.

Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.

Abstract: A comparator is disclosed, for comparing a first input voltage with a second input voltage and generating a corresponding output voltage. The comparator includes a follower stage coupled to a first supply rail and a second supply rail, a follower stage input terminal for the second input voltage, and a follower stage output terminal. The comparator also includes an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal for the first input voltage, and an inverter stage output terminal for providing an inverter stage output voltage having a first range. A signal conditioning means is coupled to the inverter stage output terminal and generates a comparator output voltage at a comparator output terminal having a second range larger than the first range.