Abstract: Image display equipment has a memory element for storing a selected combinatorial function of a cursor pattern and image field existing at an addressed cursor position, and has a controllable selector for displaying, at the cursor field, either the image field or the combined cursor field and image pattern. A single display memory can store the image field, the cursor pattern, and the selected combination of cursor pattern and image field. Selection logic addresses the stored combination pattern in lieu of the image field to provide the desired cursor display at the addressed cursor position.

Abstract: A support for a CRT monitor provides translational movement for the monitor in two perpendicular directions. The support is on rollers for movement over a horizontal surface, and includes telescoping arms for movement in a first direction. One of the arms enters an elongate guide channel mountable on the surface and includes rollers for rolling along a vertical wall of the channel so that the support moves in a second direction perpendicular to the first. The channel includes a cover and end walls.

Abstract: A multiprocessor data processing system in which a number of independent processors can concurrently operate on a shared memory even when one processor is performing a read-modify-write (RMW) operation, the system having a locking, content-associative write buffer and a controller for identifying RMW requests, for addressing the buffer and, for issuing directives to lock the buffer, to validate particular data blocks in the buffer and to transfer data back and forth between the processors, the memory and the buffer.

Abstract: A display terminal device including a tilt and swivel coupling mechanism coupling the display portion to the base portion. The coupling mechanism includes a swivel plate rotatable about a vertical neck extending from the base portion. The swivel plate includes a cylindrical top surface on which a complementary cylindrical surface of the display portion is seated. The cylindrical surfaces are spring biased toward each other by a spring mounted on a fastener extending from the display portion to the swivel plate. A horizontal fastener extends from the housing through horizontal slots in the neck.

Abstract: Disclosed are improved bipolar and field effect transistors having n-type silicon regions and associated electrical contacts comprising monocrystalline silicon doped with arsenic and phosphorus. The transistors are fabricated by depositing on a silicon substrate a coating of amorphous silicon comprising a first layer heavily doped with phosphorus and a second layer below the first doped with arsenic. Energy is selectively applied to melt the coating. As the coating resolidifies and cools, arsenic diffuses into the substrate to form shallow n-type regions which are annealed by heat from the coating. Heavily phosphorus-doped, conductive monocrystalline silicon forms above the n-type regions on the substrate, whereas polycrystalline silicon forms above dielectric or other materials. Selective removal of the polysilicon yields shallow, annealed n-type regions integral with self-registered contacts. The resulting transistors have low RC time constants and low contact resistance.

Abstract: A ring communications system having a double ring format where the integrity of both rings is continuously checked, and where repair of the network is automatically accomplished upon the detection of the return to operation of a defective ring.

Abstract: A communications network including a plurality of terminals coupled together to provide a unidirectional communications ring. Each of the terminals is coupled in series along the ring. Each terminal is adapted to transmit (at an associated data rate) a digital signal to the next downstream terminal on the ring. Each terminal is adapted to receive a digital signal at the data rate associated with the next upstream terminal. The received digital signal is applied to a phase locked loop characterized by a hold time which exceeds its lock time. The phase locked loop extracts a local timing signal for re-clocking the received digital signal. The transmission time of N bits is less than the hold time of the phase locked loop. Each terminal monitors the re-clocked signal to identify when same valued consecutive bits are received for a period less than the phase locked loop hold time, and upon such detection to cause that terminal to generate at least one transition.

Abstract: Apparatus is disclosed for reading phase encoded digital data from a nine-track magnetic tape which apparatus includes timing circuitry for deriving a clock signal from the recorded data. A portion of the timing circuitry is associated with each track on the tape and automatically accommodates, without generating errors, phase changes in the derived clock signal in that track caused by speed variations in the magnetic tape transport and due to bit shifts caused by certain data patterns.Tape transport speed variations are sensed and the derived clock rate is corrected by a digital phase-locked loop which uses a counter that is clocked at a constant rate to determine the timing "window" during which the circuitry looks for signal transitions on the magnetic tape. A running average of the count remaining in the counter at the time when a transition actually occurs is used to adjust the counter starting value until equilibrium is established.

Abstract: A communications network including a plurality of terminals coupled together to provide a unidirectional communications ring. Each of the terminals is adapted to transmit (at an associated fixed data rate) a digital signal to the next downstream terminal on the ring. Each terminal is adapted to receive a digital signal at the data rate associated with the next upstream terminal. In each local terminal, there is a detector for detecting the received synchronization packets and associated data packets are generated for transmission to the next downstream terminal on the ring at a predetermined fixed data rate associated with the local terminal. The data of each transmitted data packet matches bit for bit the data of the corresponding received data packet.

Abstract: A high speed arrangement for detecting the occurrence of a flag character in a stream of serial digital data signals employs a pattern register in which are stored the bits of the referene flag pattern. As each bit of the serial data is received, it is simultaneously compared by a set of comparators with each of the bits in the flag pattern. The first comparator of the set compares the data bit with the first bit of the flag pattern and each successive comparator compares the data bit with the next successive bit in the pattern. The outputs of the comparators are coupled to corresponding stages of a shift register in the same ordered sequence as the comparators. All the stages of the shift register are arranged to be simultaneously clocked by clock signals.

Abstract: A power supply circuit having a higher power factor and decreased current crest factor. The circuit preferably comprises an input circuit for receiving an input AC voltage and rectifying this voltage and an output circuit for providing a DC output voltage. A pulse-width-modulation circuit intercouples between the input and output circuits and includes a controlled circuit adapted to pass input AC current in pulse-wide increments with the pulse-width varying in inverse proportion to the AC voltage. In this manner, when the instantaneous AC voltage is low, the pulse widths are wider and conversely when the voltage is high, the pulse widths are narrower. In one version of the invention, the pulse width modulation is carried out by a programmed variable ratio transformer.

Abstract: A high speed data buffer array allocation circuit is provided in association with a plurality of buffer memories for directing high speed data into the memories. The circuitry employs high speed MOS technology to implement high speed switching and data allocation. The data packet input, generally from an uninterruptible source, is directed and written into a first available buffer memory. The memory can thereafter be read by a host computer. Flags are set indicating the availability of the memory for reading. The data buffer allocation circuit has a plurality of selection circuits connected in an ordered linear array for effectively passing therethrough to the circuit associated with the first available buffer, a data ready input signal. In response to the data ready input signal, the selection circuit and associated gating circuit provide the necessary control to direct the data to the associated memory and to thereafter leave a flag indicating the availability of data.

Abstract: A token-passing, ring-based data communications network provides a distributive method and apparatus for detecting and regenerating a lost token. The method includes, after detection of the loss of the token, transmitting at a detecting node a data packet not including a token, the data packet uniquely identifying the transmitting node as the data source. Simultaneously, the transmitting node, after transmitting the tokenless data packet, strips all incoming data from the network. If the transmitted packet is successfully received by the transmitting node, a new token is generated by the node. If the packet is not received, the node defers to an arbitration method which includes delaying a next data packet transmission for a probabilistically determined period of time. The mean time upon which the probabilistic approach is based increases with each unsuccessful data packet transmission attempt.