Abstract: A bus driver circuit divides an internal data bus for an integrated circuit memory into at least two groups, designated by speed. A faster group of data lines and a slower group of data lines are placed in an interleaved fashion in order to provide a two group shielding solution. At the earliest opportunity following the reception of a read command, the data from memory banks in the memory is sorted into these two groups. For a DDR3 memory, the sorting method is based on the A2 column address, known as C2. All of the data is brought out of the banks in parallel and sorted as it enters the main amplifiers. These main amplifiers are also divided into two groups, faster and slower. Each amplifier then connects to a data line (G-line) of the same group. The clock assigned to the fast group fires right away, thereby connecting the data associated with the fast amplifiers to the fast data group. This data group then proceeds to the output buffers through the entire data path as fast as possible.

Abstract: A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein.

Abstract: A panoramic camera system is disclosed that includes an unified optical system, an image capture device, and a processing unit. The unified optical system may include a first set of lenses that guide images received from horizontal directions of a target scene that surrounds the unified optical system. The unified optical system may also include a deflecting device that deflects the images guided through the first set of lenses and a second set of lenses that projects the images deflected by the deflecting device. The image capture device collects the projected images into a determined pattern based on the second set of lenses. Moreover, the processing unit processes the collected images from the image capture device to generate at least one of image signals and video signals representing a panoramic rendition of the target scene.

Abstract: Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C.

Abstract: A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material.

Abstract: A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias to the control gate directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.

Abstract: A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on the mask pattern. Next, a plurality of scattering bar reference sets is applied to the image simulation model so as to generate a plurality of simulation images, respectively. Further, a portion of the simulation images are selected to be a plurality of candidate layouts according to a screening criterion. Next, one of the candidate layouts is determined to be a pattern layout according to a selection rule, and the scattering bar reference set corresponding to the pattern layout is determined to be a scattering bar rule of the mask pattern.

Abstract: A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein.

Abstract: A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein.

Abstract: A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed.

Abstract: A phase change memory device is provided. The phase change memory device comprises a substrate. An electrode layer is on the substrate. A phase change memory structure is on the electrode layer and electrically connected to the electrode layer, wherein the phase change memory structure comprises a cup-shaped heating electrode on the electrode layer. An insulating layer is on the cup-shaped heating electrode along a first direction covering a portion of the cup-shaped heating electrode. An electrode structure is on the cup-shaped heating electrode along a second direction covering a portion of the insulating layer and the cup-shaped heating electrode. A pair of double spacers is on a pair of sidewalls of the electrode structure covering a portion of the cup-shaped heating electrode, wherein the double spacer comprises a phase change material spacer and an insulating material spacer on a sidewall of the phase change material spacer.

Abstract: An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region.

Abstract: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Abstract: A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell architecture disclosed has significant advantages over conventional designs in terms of power, radiation hardness and speed and does not require intermediate supply voltage bitline precharge while allowing for 6F2 memory cell layouts.

Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g.

Abstract: A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep trench capacitor arranged in an S-shape manner with respect to the contact plug structure via a doped region isolated by a shallow trench isolation structure. Preferably, the body portion and the two leg portions can be made of the same conductive material selected from the group consisting of polysilicon, doped polysilicon, tungsten, copper and aluminum, while the dielectric block can be made of material selected from the group consisting of borophosphosilicate glass. Particularly, the contact plug can be prepared by dual-damascene technique. Since the overlapped area between the contact plug structure and a word line can be dramatically decreased, the bit line coupling (BLC) can be effectively reduced.

Abstract: A method of stacking wafers includes: providing a first wafer including a first metal connection layer; forming a first passivation layer over the first metal connection layer; forming a first bondpad in the first passivation layer to form a first bondpad layer; providing a second wafer including second metal connection layer; forming a second passivation layer over the second metal connection layer; forming a second bondpad in the second passivation layer to form a second bondpad layer; forming at least one of a first conductive adhesive layer over the first bondpad layer and a second conductive adhesive layer over the second bondpad layer; and stacking the second wafer on the first wafer by bonding respective faces of the second bondpad layer with the first bondpad layer via the at least one of the first conductive adhesive layer and the second conductive adhesive layer.

Abstract: A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether these skews arise from reference voltage variation, data pattern loading, power supply droop, process variations within the chip itself, or other causes. The differential input strobes of the data capture circuit are input into individual input buffers, each compared against a reference voltage individually, as well as a data input pin. The outputs from these buffers are maintained separate from each other all the way to the point where the input data is latched. In latching the input data, data ones are latched entirely based on input signals derived from a rising edge (both strobes and data), and zeros are latched entirely based on input signals derived from a falling edge (both strobes and data).

Abstract: A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of ‘k’ bits. The controller only requires information regarding the value of the number ‘k’ and the pre-programmed stop code in order to control any number of bits in a shift chain.

Abstract: A configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM. The DLL design and technique disclosed employs a hybrid analog/digital delay line, but does not use conventional closed loop architecture during the digital phase of the locking process.