Patents Assigned to PROTEANTECS LTD.
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Patent number: 11929131Abstract: A memory circuit which includes: A synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines. A margin agent, determining a status of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on a signal derived from a bit line due to a signaling on at least one of the address lines. In another aspect, a memory cell, having a bit line configured to provide data input/output to the memory cell may be provided with a comparator, comparing a voltage on the bit line with a reference voltage and indicating of a status of the memory cell thereby. Firmware may receive the indication of the status of a memory cell array, and transmit the indication, issue an alert, and/or reconfigure the memory circuit responsive to the status.Type: GrantFiled: December 3, 2020Date of Patent: March 12, 2024Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Guy Redler, Evelyn Landman
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Patent number: 11841395Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: GrantFiled: July 11, 2022Date of Patent: December 12, 2023Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Shai Cohen, Yahel David, Eyal Fayneh, Inbar Weintrob
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Patent number: 11815551Abstract: An I/O sensor including: a programmable delay line; a delayed clocked receiver having the following inputs: (a) a data signal and a reference voltage that also serve as inputs to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed clocked receiver and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.Type: GrantFiled: December 27, 2022Date of Patent: November 14, 2023Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Guy Redler, Evelyn Landman
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Patent number: 11762013Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.Type: GrantFiled: April 16, 2019Date of Patent: September 19, 2023Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Yahel David, Eyal Fayneh, Shai Cohen, Yair Talker
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Patent number: 11762789Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: GrantFiled: January 31, 2022Date of Patent: September 19, 2023Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Evelyn Landman, Shai Cohen, Guy Redler, Inbar Weintrob
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Patent number: 11740281Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.Type: GrantFiled: March 24, 2022Date of Patent: August 29, 2023Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Edi Shmueli, Alexander Burlak, Evelyn Landman, Inbar Weintrob, Yahel David, Shai Cohen, Guy Redler
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Patent number: 11619551Abstract: A thermal sensor for an integrated circuit including: a Proportional To Absolute Temperature (PTAT) circuit comprising n-type MOS transistors and providing a first voltage; and a voltage generator circuit comprising a p-type MOS transistor and providing a second voltage. A reference voltage is based on the first voltage and the second voltage. At least one thermal output signal is based on the reference voltage together with the first voltage and/or the second voltage. In another aspect, an integrated circuit has a power routing arrangement, providing a power supply core voltage (VDDcore) to operate functional circuitry on the integrated circuit. One or more local thermal sensors are located on the integrated circuit, each comprising a PTAT circuit having MOS transistors using the power supply core voltage to generate a temperature-dependent voltage that varies independently of power supply core voltage variation.Type: GrantFiled: May 23, 2022Date of Patent: April 4, 2023Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Guy Redler, Shaked Rahamim, Evelyn Landman
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Patent number: 11408932Abstract: Determination of one or more operating conditions (leakage current, temperature and/or workload) of a functional transistor in a semiconductor integrated circuit (IC). The functional transistor provides an electrical current, which is provided as an input to a ring oscillator (ROSC). The ROSC is located in the IC proximate to the functional transistor and has an oscillation frequency in operation. The one or more operating conditions of the functional transistor are determined based on the oscillation frequency of the ROSC.Type: GrantFiled: January 8, 2019Date of Patent: August 9, 2022Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Inbar Weintrob, Evelyn Landman, Yahel David, Shai Cohen, Guy Redler
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Patent number: 11391771Abstract: A semiconductor integrated circuit (IC) comprising a time-to-digital converter circuit (TDC), wherein time inputs to the TDC are (i) one or more input to an input/output (I/O) buffer of a pad of the IC, and (ii) one or more output from the I/O buffer. The IC comprises a digital comparator circuit electrically configured to: receive a stream of digital output values from the TDC, compare each value of the stream to one or more previous value in the stream, and when the comparison reflects a difference value greater than a threshold, issuing a notification to a user of the IC.Type: GrantFiled: November 22, 2018Date of Patent: July 19, 2022Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Shai Cohen, Evelyn Landman, Yahel David, Inbar Weintrob
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Patent number: 11385282Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: GrantFiled: November 15, 2018Date of Patent: July 12, 2022Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Shai Cohen, Yahel David, Eyal Fayneh, Inbar Weintrob
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Patent number: 11293977Abstract: An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.Type: GrantFiled: March 18, 2021Date of Patent: April 5, 2022Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Guy Redler, Evelyn Landman, Ishai Zeev Cohen, Shaked Rahamim, Alex Khazin
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Patent number: 11275700Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: GrantFiled: August 10, 2020Date of Patent: March 15, 2022Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Evelyn Landman, Shai Cohen, Guy Redler, Inbar Weintrob
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Patent number: 11132485Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.Type: GrantFiled: June 19, 2019Date of Patent: September 28, 2021Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Yair Talker, Eyal Fayneh, Yahel David, Shai Cohen, Inbar Weintrob
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Patent number: 10740262Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: GrantFiled: December 30, 2019Date of Patent: August 11, 2020Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Evelyn Landman, Shai Cohen, Guy Redler, Inbar Weintrob