Abstract: Instructions of a program are stored in compressed form in a program memory (12). In a processor which executes the instructions, a program counter (50) identifies a position in the program memory. An instruction cache (40) has cache blocks, each for storing one or more instructions of the program in decompressed form. A cache loading unit (42) includes a decompression section (44) and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. A cache pointer (52) identifies a position in the instruction cache of an instruction to be fetched for execution. An instruction fetching unit (46) fetches an instruction to be executed from the position identified by the cache pointer.

Abstract: A microelectromechanical structure is formed by depositing sacrificial and structural material over a substrate to form a structural layer on a component electrically attached with the substrate. The galvanic potential of the structural layer is greater than the galvanic potential of the component. At least a portion of the structural material is covered with a protective material that has a galvanic potential less than or equal to the galvanic potential of the component. The sacrificial material is removed with a release solution. At least one of the protective material and release solution is surfactanated, the surfactant functionalizing a surface of the component.

Abstract: A processor which is switchable between a first execution mode (such as a scalar mode) and a second execution mode (such as a VLIW mode) is disclosed. The processor has a first processor context when in the first execution mode and a second processor context, different from the first processor context, when in the second execution mode. The processor generates an exception when the processor attempts to change from one execution mode to the other. When the processor switches to a thread of execution which is in the first execution mode, or when the processor switches to a thread of execution which was the last thread to be in the second execution mode, only the first processor context is preserved. The processor may be arranged such that the number of threads that may be in the second execution mode at any one time is less than the total number of threads that may be active on the processor at any one time.

Abstract: A microelectromechanical structure is formed by depositing sacrificial and structural material over a substrate to form a structural layer on a component electrically attached with the substrate. The galvanic potential of the structural layer is greater than the galvanic potential of the component. At least a portion of the structural material is covered with a protective material that has a galvanic potential less than or equal to the galvanic potential of the component. The sacrificial material is removed with a release solution. At least one of the protective material and release solution is surfactanated, the surfactant functionalizing a surface of the component.

Abstract: A processor has respective first and second external instruction formats (F1, F2) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F1: i+1˜i+4; F2: i+1˜i+3) in which the opcode appears. The processor also has an internal instruction format (G1) into which instructions in the external formats are translated prior to execution of the operation. A first operation (add) is specifiable in both the first and second external formats F1, F2), and a second operation (load) is specifiable in the second external format (F2). The first and second operations have distinct opcodes (101, 011) in the second external format. In each of the preselected opcode bits which the first and second external formats have in common (i+1˜i+3), the opcodes of the first operation (101) in the two external formats are identical.

Abstract: Instructions of a program are stored in compressed form in a program memory. A cache loading unit includes a decompression section and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. When a cache miss occurs because the instruction to be fetched is not present in the instruction cache, a cache loading unit performs such a cache loading operation. An updating unit updates the program counter and cache pointer in response to the fetching of instructions so as to ensure that the position identified by the said program counter is maintained consistently at the position in the program memory at which the instruction to be fetched from the instruction cache is stored in compressed form.

Abstract: An electromechanical system includes a structural plate in contact with a stop and an actuator activated by a force for creating a movement of the stop relative to the structural plate, wherein the movement is sufficient to overcome stiction forces between the structural plate and the stop.

Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.

Abstract: Efficient techniques for computation of texture coordinates using scaled conversion operations for a 3D graphics pipeline utilizing a scaled floating point to integer instruction and a scaled integer to floating point instruction to significantly reduce memory requirements. A parallel array VLIW digital signal processor is employed along with specialized scaled conversion instructions and communication operations between the processing elements, which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the graphics pipeline hardware to be efficiently used.

Abstract: Video data is compressed with nonkey frames encoded with reference to segmentation of reference frames, where the encoded video data includes kinetic information relating segments of a reference frame to pixels of a nonkey frame and the kinetic information includes translations of segments and at least one of a z-order, a deformation and a lighting change. The segmentation performed during encoding can be included in whole or part in the compressed video data. If used, z-ordering could be relative or absolute, based on changes of occlusion of segments by other segments between the frames, based on content of other frames or based on z-order indications in the video data being compressed. Other kinetic information might include segment changes between frames such as rotation, dilation, affine transformations, nonlinear transformations defined by a set of deformation parameters, linear lighting offsets in one, two or three color planes, and/or residue information.

Abstract: An iterative process is used to set the phase prechirp of a WDM optical transport system to a system's optimal level that maximizes the signal quality. A signal degradation factor takes into account linear and non-linear effects along the optical path and is used as a receive end feedback signal to control the phase prechirp level at the transmitter site. By using the FEC corrected errors rate as the feedback signal, optimization of signal quality is performed even when the system is running error free. By using an adaptive phase prechirp transmitter, signal degradation compensation can be also performed on a per wavelength basis to compensate for the residual dispersion slope and to allow optimization of individual channels independently of the net link dispersion value.

Abstract: A process and apparatus for allocating bits between the stages of a multi-stage digital image compression scheme with quantizer feedback is disclosed. The process selects a quantization schedule (from a finite number of possibilities) for all stages that minimizes an estimate of total distortion while keeping total bit demand below a constraint; uses said schedule to actually quantize one stage of the compression scheme; selects a new quantization schedule for the remaining stages using estimates for distortion and bit demand that are updated to reflect the quantization of the previous stage; actually quantizes the next stage according to the new quantization schedule; and continues recursively until it has chosen an actual quantization scale for every stage of the compression scheme.

Abstract: Video data is compressed using segmentation of reference frames where the segmentation results in a hierarchy of segments. The hierarchy can be generated bottom-up, where a first set of segments is generated and then a second set of segments generated by grouping segments of the first set, based on pixel value and/or segment boundaries. The hierarchy can be generated top-down, where a first set is generated and then a second set is generated by dividing up segments of the first set, based on pixel value and/or segment boundaries. The hierarchy can be included in the compressed video data or omitted such that a decoder would have to independently generate it. The hierarchy can be two or more levels. The hierarchy can be used for editing, formatting and/or compressing frames, as well as associating metadata with elements of the frame and coding motion, residue or other kinetic information.

Abstract: An encoder segments frames of video data and associates metadata with segments. The metadata elements can be associated with the segments that include areas of the frame associated with the metadata elements. A motion matcher can match segments of a reference frame to pixels of a current nonkey frame being encoded when a metadata associator associates elements of metadata with segments of the segmentation of the reference frame and associates a matched segment's metadata elements with matched areas of the current frame. The metadata elements might represent actions to be taken when a user of the video data indicates a selection of an area of an image that has that metadata element associated therewith. The metadata associations can be included in the encoded video data or deduced by a decoder. The metadata associations can be independent of segment indices or other segment changes.

Abstract: A decoder decodes compressed video data wherein nonkey frames are decoded with reference to other frames from the video data that are reference frames. The decoder generates at least a part of a segmentation of the reference frames for use in decoding nonkey frames. A nonkey frame is regenerated using kinetic information about the current frame and the reference frame segmentation. Kinetic information might include segment translation information. Where the segmentation used in encoding the compressed video data can vary among a plurality of segmentation schemes, the decoder determines which segmentation scheme is used from selection indications in the compressed video data or from previously decoded video data. The decoder might also use partial segmentation information, segmentation hints, partial segment canonical information and/or canonical hints in its segmentation process. The decoder might also process segment-related metadata extracted the compressed video data.

Abstract: A coordinated method is provided for controlling dynamic gain equalization in an optical transport network. The method includes: detecting a deviation in optical power of an optical signal traversing the optical transport network along a transmission path, adjusting spectral profile of the optical signal at a first network element in the optical transport network, where the first network element is located in the transmission path downstream from the origination point of the deviation; and adjusting spectral profile of the optical signal at a second network element subsequent to the adjustment at the first network element, where the second network element is located in the transmission path downstream from the origination point and the first network element.

Abstract: A system and method for minimizing blocking in optical networks utilizes algorithms developed to reduce non-revenue generating OEO conversions as a result of blocking based on routing and wavelength and/or subband assignment. Demands are prioritized on a basis of optical reach, and regenerators required for overcoming optical reach limitations are strategically placed to overcome blocking.

Abstract: An optical wavelength cross connect is provided to receive multiple input optical signals that each have multiple spectral bands and to transmit multiple output optical signals that each have one or more of those spectral bands. The optical wavelength cross connect includes multiple wavelength routing elements, which are optical components that selectively route wavelength components between one optical signal and multiple optical signals in either direction according to a configurable state. As used within the optical wavelength cross connect, each of the wavelength routing elements receives at least one optical signal corresponding to one of the input optical signals. A mapping of the spectral bands to the output optical signals is determined by the states of the wavelength routing elements.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.

Abstract: A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The multiplier simultaneously performs multiplications to produce each combination of products between the real and imaginary terms of the first and second complex operands. The multiplexer selects which produced products are added to or subtracted from each other based on the type of complex multiplication being performed. The adder simultaneously performs additions and subtractions, if necessary, to produce both real and imaginary results depending on whether the type of complex multiplication being performed is a conjugated operation. The registers store the results of the complex multiplication.