Abstract: This invention concerns the fabrication of nano to atomic scale devices, that is electronic devices fabricated down to atomic accuracy. The fabrication process uses either an SEM or a STM tip to pattern regions on a semiconductor substrate. Then, forming electrically active parts of the device at those regions. Encapsulating the formed device. Using a SEM or optical microscope to align locations for electrically conducting elements on the surface of the encapsulating semiconductor with respective active parts of the device encapsulated below the surface. Forming electrically conducting elements on the surface at the aligned locations. And, electrically connecting electrically conducting elements on the surface with aligned parts of the device encapsulated below the surface to allow electrical connectivity and tunability of the device. In further aspects the invention concerns the devices themselves.

Abstract: The correction of errors in the transport and processing of qubits makes use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site.

Abstract: This invention concerns interfacing to electronic circuits or systems operating at low temperature or ultra-low temperature using complementary metal-oxide semiconductor (CMOS) technology. Low temperature in this case refers to cryogenic temperatures in particular, but not exclusively, to the 4.2 K region. Ultra-low temperatures here refers to the sub-1 K range, usually accessed using dilution refrigerator systems. The electronic circuits comprise a controller (for writing and manipulation), an observer (for readout and measurement) circuits, or both, fabricated from ultra-thin silicon-on-insulator (SOI) CMOS technology.

Abstract: This invention concerns semiconductor devices of the general type comprising a counted number of dopant atoms (142) implanted in regions of a substrate (158) that are substantially intrinsic semiconductor. One or more doped surface regions (152) of the substrate (158) are metallized to form electrodes (150) and a counted number of dopant ions (142) are implanted in a region of the substantially intrinsic semiconductor.

Abstract: A silicon integrated circuit device comprising a near intrinsic silicon substrate in which there are one or more ohmic contact regions. An insulating layer lies above the substrate, and on top of the insulating layer is a lower layer of one or more aluminium gates. The surface of each of the lower gates is oxidised to insulate them from an upper aluminium gate that extends over the lower gates.

Abstract: In the field of optical quantum information processing, manipulation of single photon qubits in frequency modes employs a frequency beamsplitter employs an asymmetric two-path interferometer, reversible down to the quantum limit. A first partially transmitting mirror splits photons into first and second paths. A time delay element introduces a differential time delay into the second path. And a second partially transmitting mirror mixes the two paths again to form two outputs. A half-wave plate utilizes two of the beam splitters.

Abstract: This invention concerns the fabrication of nanoscale and atomic scale devices. The method involves creating one or more registration markers. Using a SEM or optical microscope to form an image of the registration markers and the tip of a scanning tunnelling microscope (STM). Using the image to position and reposition the STM tip to pattern the device structure. Forming the active region of the device and then encapsulating it such that one or more of the registration markers are still visible to allow correct positioning of surface electrodes. The method can be used to form any number of device structures including quantum wires, single electron transistors, arrays or gate regions. The method can also be used to produce 3D devices by patterning subsequent layers with the STM and encapsulating in between.

Abstract: This invention concerns quantum computers in which the qubits are closed systems, in that the particle or particles are confined within the structure. A “site” can be produced by any method of confining an electron or other quantum particle, such as a dopant atom, a quantum dot, a cooper pair box, or any combination of these. In particular the invention concerns a closed three-site quantum particle system. The state in the third site is weakly coupled by coherent tunneling to the first and second states, so that the third state is able to map out the populations of the first and second states as its energy is scanned with respect to the first and second states. In second and third aspects it concerns a readout method for a closed three-state quantum particle system.

Abstract: This invention concerns semiconductor devices of the general type comprising a counted number of dopant atoms (142) implanted in regions of a substrate (158) that are substantially intrinsic semiconductor. One or more doped surface regions (152) of the substrate (158) are metallised to form electrodes (150) and a counted number of dopant ions (142) are implanted in a region of the substantially intrinsic semiconductor.

Abstract: This invention concerns nanoscale products, such as electronic devices fabricated to nanometer accuracy. It also concerns atomic scale products. These products may have an array of electrically active dopant atoms in a silicon surface, or an encapsulated layer of electrically active donor atoms. In a further aspect the invention concerns a method of fabricating such products. The methods include forming a preselected array of donor atoms incorporated into silicon. Encapsulation by growing silicon over a doped surface, after desorbing the passivating hydrogen. Also, using an STM to view donor atoms on the silicon surface during fabrication of a nanoscale device, and measuring the electrical activity of the donor atoms during fabrication of a nanoscale device. Such products and processes are useful in the fabrication of a quantum computer, but could have many other uses.

Abstract: Individual hydrogen atoms are desorbed from a hydrogen terminated layer on a silicon substrate, using an STM tip, to form a pattern of exposed regions. A single donor-bearing molecule (such as phosphorous atoms). The spins of the donor atoms may be used as qubits in a slid quantum computer.

Abstract: This invention concerns a method and system for single ion doping and machining by detecting the impact, penetration and stopping of single ions in a substrate. Such detection is essential for the successful implantation of a counted number of 31P ions into a semi-conductor substrate for construction of a Kane quantum computer. The invention particularly concerns the application of a potential across two electrodes on the surface of the substrate to create a field to separate and sweep out electron-hole pairs formed within the substrate. A detector is then used to detecting transient current in the electrodes, and so determine the arrival of a single ion in the substrate.