Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract: A programmable integrated circuit (see FIG. 9) has a plurality of L-shaped programming power buses (for example, 126, 130, 129 and 127) that extend along sides of the integrated circuit. Each L-shaped programming power bus extends along two adjacent sides of the integrated circuit such that legs of two L-shaped programming power buses extend along each of the sides. There are four pluralities of programming drivers (for example, 110, 117, 115 and 112), one plurality being associated with each of the four sides. There are also four programming current multiplexers (for example, 118, 125, 123 and 120), one associated with each of the sides. A programming driver of one of the plurality of programming drivers is selectively couplable to one of the two L-shaped programming power bus legs that extends along the associated side of the integrated circuit via the programming current multiplexer associated with that side.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract: A programmable integrated circuit (see FIG. 5) has a plurality of linearly extending wire segments with antifuses disposed between each wire segment and a plurality of linearly extending programming conductors that are perpendicular to the wire segments. A plurality of programming transistors are disposed between a corresponding respective one of the wire segments and a corresponding respective one of the programming conductors. A programming control conductor extending from a programming control driver is coupled to the gate electrode of each of the programming transistors as well as the gate electrode of a test transistor. A test antifuse is coupled in series with the test transistor. When the programming control conductor can drive the test transistor with an adequately high voltage to program the test antifuse, it is assumed that the programming control conductor can drive the programming transistor with an adequately high voltage to program the antifuses.

Abstract: A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse.

Abstract: The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention concerns a programmable logic device comprising a plurality of routings lines coupled to a plurality of logic blocks when programmed. During programming, a path is routed through the routing lines by programming the selected programmable elements. The selected programmable elements are located at each interconnect point between at least two routing lines or two segments of a routing lines along the path. The programmable elements include at least two interconnect circuits coupled in parallel. The programmable element is successfully programmed when at least one of the interconnect circuits is functional after programming.

Abstract: An interface cell for a programmable integrated circuit includes a pad, an input buffer, a first routing conductor, a plurality of second routing conductors, and a plurality of antifuses. The input of the input buffer is coupled to the pad and the output of the input buffer is coupled to the first routing conductor so that an input signal from the pad can be supplied onto the first routing conductor without passing through any programmed antifuses. The second routing conductors extend parallel to one another in a direction perpendicular to the direction in which the first routing conductor extends. The second routing conductors cross the first routing conductor and then pass out of the interface cell and into a routing channel of the programmable integrated circuit. One of the antifuses is disposed at each location where one of the second routing conductors crosses the first routing conductor.

Abstract: A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed.

Abstract: A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to be driven from the clock pad. An output of a selected logic cell can be coupled to the first clock bus if the clock network is to be driven from a logic cell. To increase speed of the clock network, the first clock bus is segmented (in one embodiment, collinearly extending segments can be selectively coupled together via selectively programmable antifuses) so that only a short piece of the first clock bus is used to couple either the pad or the logic cell to the clock network in high speed applications.

Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: A programmable integrated circuit such as a field programmable gate array (see FIG. 3) has a few long routing wire segments for transmitting signals long distances across the integrated circuit. These long routing wire segments can be coupled together with programmed antifuses. A high-drive output driver may be used to drive signals a long distance through such coupled together long routing wire segments giving rise to large switching currents across the programmed antifuses that couple the long wire segments together. In some types of antifuses, programmed antifuse reliability is dependent upon maintaining the programming current used to program the antifuse a certain factor greater than the peak switching current flowing through the antifuse during normal operation. The antifuses in these long wire segments therefore should be programmed with proportionately larger programming currents.

Abstract: A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.

Abstract: The programmable interconnect structure of a field programmable gate array (see FIG. 4B) includes a plurality of wire segments extending in a first direction, the wire segments being collinear with respect to each other. An antifuse is disposed between each pair of adjacent wire segments so that the adjacent wire segments can be coupled together. Programming conductors for supplying a programming voltage onto selected wire segments extend in a second direction perpendicular to the first direction. The programming drivers for driving some of the programming conductors are disposed on one side (for example above) of the wire segments whereas the programming drivers for driving others of the programming conductors are disposed on the opposite side (for example below) of the wire segments. The pattern for programming drivers coupled to programming conductors alternates from one side of the wire segments to the other from column to column across the field programmable gate array.

Abstract: A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. In one aspect, the number of programming conductors and the number of perpendicular programming control conductors for a logic module are substantially equal. In another aspect, programming current is supplied onto long routing wire segments via two programming transistors and two programming conductors. In another aspect, a pattern of programming drivers alternates from one side of the integrated circuit to the opposite side from one column of macrocells to the next. In other aspects, control conductors and programming conductors are tested with test antifuses and test transistors. In another aspect, adjacent logic modules have mirrored structures so that they can share an intervening programming conductor resource.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.

Abstract: Select sets of a logic function corresponding to an output of a first logic circuit are determined. These select sets are used to obtain a second logic circuit, the logic function corresponding to the output of which is the same as the logic function corresponding to the output of the first logic circuit. A propagation delay through the second logic circuit may be smaller than a corresponding delay through the first logic circuit. Sometimes, such a smaller propagation delay through the second logic circuit results in the second logic circuit having a smaller critical path delay. The second logic circuit may therefore have a greater maximum operating speed than the first logic circuit.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract: A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.