Abstract: An energy conversion device for conversion of chemical energy into electricity. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous catalyst material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous catalyst material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: An energy conversion device for conversion of chemical energy into electricity. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous catalyst material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous catalyst material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: An energy conversion device for conversion of various energy forms into electricity. The energy forms may be chemical, photovoltaic or thermal gradients. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The substrate itself can be planar, two-dimensional, or three-dimensional, and possess internal and external surfaces. These substrates may be rigid, flexible and/or foldable. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous conductor material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous conductor material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: An energy conversion device for conversion of various energy forms into electricity. The energy forms may be chemical, photovoltaic or thermal gradients. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The substrate itself can be planar, two-dimensional, or three-dimensional, and possess internal and external surfaces. These substrates may be rigid, flexible and/or foldable. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous conductor material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous conductor material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: An energy conversion device for conversion of various energy forms into electricity. The energy forms may be chemical, photovoltaic or thermal gradients. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The substrate itself can be planar, two-dimensional, or three-dimensional, and possess internal and external surfaces. These substrates may be rigid, flexible and/or foldable. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous conductor material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous conductor material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: An energy conversion device for conversion of chemical energy into electricity. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous catalyst material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous catalyst material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: An energy conversion device for conversion of chemical energy into electricity. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous catalyst material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous catalyst material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: An energy conversion device for conversion of chemical energy into electricity. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous catalyst material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous catalyst material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: The present disclosure relates to a nanopillar tunneling photovoltaic (“NPTPV”), and method for fabricating it. The NPTPV device has a regular array of semiconductor pillar cores formed on a substrate having a conductive surface. Layers of high-k material are formed on the cores to provide an efficient tunneling layer for electrons (or holes) generated by incident photons in the cores. Transparent conductive collector layers are formed on the tunneling layer to collect the tunneled carriers. An optimized deposition process, various surface preparations, an interfacial layer between the pillars and the high-k tunnel layer, and optimized pre- and post-deposition annealing reduce the interface trap density and thus reduce recombination prior to tunneling. The absence of a junction also reduces core recombination, resulting in a high short-circuit current. Modifying the collector material and core doping tunes the open-circuit voltage. Such NPTPVs result in large-scale low-cost PVs.

Abstract: An energy conversion device for conversion of various energy forms into electricity. The energy forms may be chemical, photovoltaic or thermal gradients. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The substrate itself can be planar, two-dimensional, or three-dimensional, and possess internal and external surfaces. These substrates may be rigid, flexible and/or foldable. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous conductor material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous conductor material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: An energy conversion device for conversion of chemical energy into electricity. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The porous semconductor or dielectric layer can be a nano-engineered structure. A porous catalyst material is placed on at least a portion of the porous semconductor or dielectric layer such that at least some of the porous catalyst material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

Abstract: The present disclosure relates to a nanopillar tunneling photovoltaic (“NPTPV”), and method for fabricating it. The NPTPV device has a regular array of semiconductor pillar cores formed on a substrate having a conductive surface. Layers of high-k material are formed on the cores to provide an efficient tunneling layer for electrons (or holes) generated by incident photons in the cores. Transparent conductive collector layers are formed on the tunneling layer to collect the tunneled carriers. An optimized deposition process, various surface preparations, an interfacial layer between the pillars and the high-k tunnel layer, and optimized pre- and post-deposition annealing reduce the interface trap density and thus reduce recombination prior to tunneling. The absence of a junction also reduces core recombination, resulting in a high short-circuit current. Modifying the collector material and core doping tunes the open-circuit voltage. Such NPTPVs result in large-scale low-cost PVs.