Patents Assigned to Rambus Inc.
  • Patent number: 11843372
    Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: December 12, 2023
    Assignee: Rambus Inc.
    Inventor: Huy Nguyen
  • Patent number: 11836099
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Grant
    Filed: December 11, 2021
    Date of Patent: December 5, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Patent number: 11836044
    Abstract: A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: December 5, 2023
    Assignee: Rambus Inc.
    Inventor: John Eric Linstadt
  • Patent number: 11829640
    Abstract: A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: November 28, 2023
    Assignee: Rambus Inc.
    Inventor: Srinivas Satish Babu Bamdhamravuri
  • Patent number: 11829307
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: November 28, 2023
    Assignee: Rambus Inc.
    Inventors: Liji Gopalakrishnan, Frederick A. Ware, Brent S. Haukness
  • Patent number: 11830573
    Abstract: A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship been the control signal and the timing signal.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: November 28, 2023
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Patent number: 11829308
    Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: November 28, 2023
    Assignee: Rambus Inc.
    Inventors: Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
  • Patent number: 11822822
    Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: November 21, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Thomas Vogelsang
  • Patent number: 11823732
    Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: November 21, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Suresh Rajan, Scott C. Best
  • Patent number: 11823757
    Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: November 21, 2023
    Assignee: Rambus Inc.
    Inventors: Craig Hampel, Mark Horowitz
  • Patent number: 11823734
    Abstract: A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 21, 2023
    Assignee: Rambus Inc.
    Inventor: Thomas Vogelsang
  • Patent number: 11815940
    Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: November 14, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Kenneth L. Wright
  • Patent number: 11816047
    Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: November 14, 2023
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Thomas J. Giovannini
  • Patent number: 11809345
    Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: November 7, 2023
    Assignee: Rambus Inc.
    Inventors: Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
  • Patent number: 11809712
    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: November 7, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern
  • Patent number: 11811379
    Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: November 7, 2023
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Carl W. Werner
  • Patent number: 11811397
    Abstract: An signal switching integrated-circuit die includes an array of switch cells, control signal contacts, data input contacts and data output contacts. Switch control signals are received from an external control-signal source via respective control signal contacts, inbound data signals are received from one or more external data-signal sources via respective data input contacts and outbound data signals are conveyed to one or more external data-signal destinations via respective data output contacts. The array of switch cells receives the control signals directly from the control signal contacts and response to the control signals by switchably interconnecting the data input contacts with selected ones of the data output contacts.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: November 7, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Carl W. Werner
  • Patent number: 11804259
    Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: October 31, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Zhichao Lu, Kenneth Lee Wright
  • Patent number: 11803489
    Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: October 31, 2023
    Assignee: Rambus Inc.
    Inventors: Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
  • Patent number: 11803328
    Abstract: An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: October 31, 2023
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware