Patents Assigned to Ramton International Corporation
  • Multibus cached memory system
    Patent number: 5802560
    Abstract: A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: September 1, 1998
    Assignee: Ramton International Corporation
    Inventors: James Dean Joseph, Doyle James Heisler, Dion Nickolas Heisler