Abstract: A symmetrical square wave, having zero average value, is coupled to the input of a horizontal deflection yoke through an S-shaping capacitance. A negative resistance coupled to the output of the yoke has a negative resistance value which compensates for resistive losses in the yoke. A yoke current generated in the yoke will be a symmetrical triangular waveform. A first control loop adjusts the negative resistance value to assure successive zero value crossings of the yoke current are coincident in time with each center of successive horizontal scan lines. A second control loop adjusts the square wave to assure successive level transitions of the square wave are coincident in time with successive changes of scanning direction.

Abstract: A television display system employing edge brightness flicker reduction by modulation of the vertical deflection signal has digital control words for modulation polarity (D) and magnitude (S). These digital words are coupled to an amplifier (900) and converted to a bipolar analog signal (Bp). The bipolar analog signal comprises values in a first and second range. Signals in the first range produce vertical deflection modulation in a first direction and signals in the second range produce vertical deflection modulation in the opposite direction.

Abstract: A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.

Abstract: A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.

Abstract: Video signal compression apparatus includes a memory for storing two fields of image data and providing fields of image data separated by one frame intervals. Frames of video signal are composed from the respective ones of the fields. The field types (e.g., odd or even) of respective fields are determined. Flags are associated with composed frames to indicate if a field of respective frames may be repeated upon reproduction, and which field of the composed frames should be displayed first.

Abstract: A method and apparatus for generating an interactive component data stream, representing an application program, for an audio video interactive (AVI) composite signal, is disclosed. The method comprises the following steps. First, program files representing the application program are generated. Then, flow data defining the data structure of the interactive component is generated. Finally the data stream is generated by selectively inserting program files into the data stream in response to the flow data. Apparatus for generating such an interactive component data stream comprises a source of program files representing the application program and a source of flow data defining the data structure of the interactive component. A flow builder selectively inserts files from the source of files into the interactive component in response to data from the flow data source.

Abstract: A phase detector of a phase-lock-loop circuit measures a phase error between an output signal of an oscillator and a synchronizing signal. When a difference between the phase error that is measured in a pair of horizontal line periods exceeds a first magnitude, that is indicative of phase error inconsistency, the phase of the oscillator output signal is not corrected and the phase-lock-loop circuit operates in an idle mode of operation.

Abstract: In a phase-lock-loop circuit a frequency detector measures a frequency error between an oscillatory signal and a synchronizing signal in alternate horizontal line periods for generating a frequency error indicative signal. The frequency error indicative signal is applied to an oscillator for correcting the frequency error in other alternate horizontal line periods in a manner to prevent frequency error measurement and correction from occurring in the same horizontal line period.

Abstract: A vertical panning system comprises: a source of respective signals having a vertical synchronizing frequency, a horizontal synchronizing frequency and a multiple of the horizontal synchronizing frequency; a video display having an interlaced field mode of operation; a horizontal display control circuit coupled to the video display and responsive to the supplied horizontal synchronizing frequency signal; a digital phase delay circuit, responsive to the supplied multiple horizontal synchronizing frequency signal, the supplied vertical synchronizing frequency signal and to a panning control signal, having as an output a second vertical synchronizing frequency signal delayed in phase relative to the supplied vertical synchronizing frequency signal by any one of a plurality of delays differing in increments corresponding in duration to horizontal half line intervals; and, a vertical display control circuit coupled to the video display and responsive to the second vertical synchronizing frequency signal.

Abstract: Video signal compression apparatus includes a memory for storing two fields of image data and providing fields of image data separated by one frame intervals. Image data from corresponding fields of successive frames are subtracted to generate field differences. The field differences are accumulated over respective field intervals, and the sum is compared against a predetermined value. If a sum of differences over a field is less than the predetermined value, the most recent field is considered to be redundant and may be excised. After respective fields are excised, frames of video signal are composed from the remaining fields. The field types (e.g., odd or even) of the fields in the memory are determined, and the data is accessed from the respective fields in memory such that data from odd and even fields occupy odd and even lines in the composed frames respectively.

Abstract: A deflection apparatus produces a field gradient that reduces a tendency of a major axis of a beam spot to become elongated at each corner, at each end of a horizontal axis and at each end of a vertical axis of a display screen relative to the beam spot at the center of the display screen. A beam spot stigmator causes the beam spot to be substantially anastigmatic at each of the corners, the end of the horizontal axis and the end of the vertical axis of the display screen.

Abstract: Apparatus for developing synchronization of an intermediate layer of signal such as the transport or multiplex layer of a multi-layered compressed video signal, includes at the encoding end of the system apparatus for including a time stamp reference, such as a count value from a modulo K counter, and provision for a differential time stamp which may be updated by the transit times of respective (e.g., multiplexing) circuits as the signal transits such circuits. At the receiving end of the system a counter is responsive to a controlled receiver clock signal and the count value of this counter is sampled at the arrival of the time stamps embedded in the transport layer. The time stamps and the differential time stamps are retrieved from the signal and combined to form a corrected time stamp. The differences of successive sampled count values of the receiver counter are compared with the differences of corresponding successive corrected time stamps to provide a signal to control the receiver clock signal.

Abstract: Apparatus for developing synchronization of an intermediate layer of signal such as the transport or multiplex layer of a multi-layered compressed video signal, includes at the encoding end of the system apparatus for including a time stamp reference, such as a count value from a modulo K counter, and provision for a differential time stamp which may be updated by the transit times of respective (e.g., multiplexing) circuits as the to signal transits such circuits. At the receiving end of the system a counter is responsive to a controlled receiver clock signal and the count value of this counter is sampled at the arrival of the time stamps embedded in the transport layer. The time stamps and the differential time stamps are retrieved from the signal and combined to form a corrected time stamp. The differences of successive sampled count values of the receiver counter are compared with the differences of corresponding successive corrected time stamps to provide a signal to control the receiver clock signal.

Abstract: A video input signal is amplified and applied to the cathode of a kinescope via linear kinescope driver amplifier provided with an output impedance sufficiently high to impart gamma correction to images displayed by the kinescope but tending to diminish the bandwidth of the amplified video signal applied to the cathode. A capacitor is included in the driver for restoring the bandwidth of the amplified video signal. For stabilizing the high frequency response (detail) of displayed images the value of the capacitor is varied as a function of the brightness of displayed images.

Abstract: A digital video signal processing system includes apparatus for concealing errors which might occur in reproduced images due to image data lost during signal transmission. The system includes circuitry for detecting transmitted video data, generating error signals if errors are present in segments (transport blocks) of the received data, and excising segments having errors from the data stream. The received data is applied to a decoder/decompressor system which decodes and decompresses the transmitted video data according to a predetermined sequence and applies the decompressed video data to a memory (for subsequent display or recording, etc.). The decompressor is responsive to the error signals for altering the predetermined sequence.

Abstract: A video signal compression system includes motion compensated predictive compression apparatus for compressing respective frames of video signal according to either intraframe processing or interframe processing on a block by block basis to generate blocks of compressed data and associated motion vectors. A compressed signal formatter arranges the blocks of compressed data and the associated motion vectors according to a desired signal protocol wherein motion vectors of interframe processed frames are associated with corresponding blocks of compressed data and motion vectors of intraframe processed frames are associated with blocks substantially adjacent to corresponding blocks of compressed data. The motion vectors are included with intraframe compressed data to facilitate error concealment at respective receiver apparatus.

Abstract: Video signal compression apparatus includes a memory for storing two fields of image data and providing fields of image data separated by one frame intervals. Image data from corresponding fields of successive frames are subtracted to generate field differences. The field differences are accumulated over respective field intervals, and the sum is compared against a predetermined value. If a sum of differences over a field is less than the predetermined value, the most recent field is considered to be redundant and may be excised. After respective fields are excised, frames of video signal are composed from the remaining fields. The field types (e.g., odd or even) of the fields in the memory are determined, and the data is accessed from the respective fields in memory such that data from odd and even fields occupy odd and even lines in the composed frames respectively.

Abstract: A rate controlled VBR quantizing system includes a quantizer for quantizing partially compressed video data and further apparatus for monitoring the amount of compressed output data. Dependent upon the amount of compressed output data being lesser or greater than a predetermined value, the quantizer is conditioned to operate in a fixed quantization mode, or a mode wherein only selected blocks of data in respective frames are adaptively quantized, respectively.

Abstract: A phase-lock-loop circuit for generating a clock signal at a frequency higher than a horizontal frequency of a video signal includes a phase detector. The phase detector includes a flip-flop that is set when a horizontal sync pulse occurs. An output of a counter that provides frequency division is decoded for resetting the flip-flop in each horizontal period. Other than for the flip-flop, and for the counting stages of the counter, only combinational logic components are used for producing a phase error indicative signal that is coupled via a low-pass filter to a control input of an oscillator of the phase-lock-loop circuit.

Abstract: The present invention provides an improved color picture tube having a viewing screen and a shadow mask mounted adjacent to the screen. The mask has an apertured contoured portion and a peripheral skirt. The improvement comprises the skirt having a reverse bend therein, wherein a first portion of the skirt that connects with the apertured contoured portion extends away from the screen and a second portion of the skirt more remote from the apertured contoured portion extends towards the screen.