Abstract: A computationally efficient method for minimizing the visible effects of texture LOD transitions across a polygon. The minimization is accomplished by adding a dithering offset value to the LOD value computed for each pixel covered by a graphics primitive to produce a dithered pixel LOD value. The dithering offsets mat be generated from a table look-up based on the location of the pixel within a span of pixels. The dithered pixel LOD value is used to as an index in the selection of a single LOD texture map from which a textured pixel value is retrieved. The range of dithering offset values can be adjusted by modulating the values in the table look-up.

Abstract: The invention, in one embodiment, is a method for performing direct memory access. The method includes arbitrating between a chained, low priority, direct memory access and a high priority, direct memory access, the arbitration occurring between two links in the chained, low priority, direct memory access.

Abstract: Anisotropically mapping of texture information to each pixel required for display of each of plural polygons forming each scene on a CIG display in a computational efficient manner, uses the footprint of each transformed pixel silhouette, as mapped from image space into the texture array, to determine an anisotropic texture space area having both a related length and a related width, in which complete texels and texels fractions are covered by that pixel footprint. A set of un-normalized line equations characterizing a particular pixel footprint is used to determine whether each texel or subtexel in the vicinity of that pixel footprint is either enclosed or avoided by (i.e. inside or outside of) that projected pixel footprint.

Abstract: In a computer image generation system, a method for reducing page switches when rendering polygons to a color and Z-buffer using a memory subsystem with N banks of memory. The method is performed by first allocating the pages of a first memory subsystem (Z-buffer or color) to consecutive and contiguous pages of the frame buffer memory, where the individual frame buffer memory pages reside in one of N banks of memory. The second memory subsystem(Z-buffer or color)is then allocated according to the following rule: the allocation of the second memory subsystem is made such that its first page does not reside in a memory bank whose index is equal to the index of the memory bank allocated to the first page of the memory subsystem. The allocation rule effectively reduces page switches by virtue of being able to access different memory banks for both Z-buffer and color read and writes thereby by avoiding the computational costs associated with opening multiple memory pages in the same memory bank.

Abstract: A rasterizer comprised of a bounding box calculator, a plane converter, a windower, and incrementers. For each polygon to be processed, a bounding box calculation is performed which determines the display screen area, in spans, that totally encloses the polygon and passes the data to the plane converter. The plane converter also receives as input attribute values for each vertex of the polygon. The plane converter computes planar coefficients for each attribute of the polygon, for each of the edges of the polygon. The plane converter unit computes the start pixel center location at a start span and a starting coefficient value at that pixel center. The computed coefficients also include the rate of change or gradient, for each polygon attribute in the x and y directions, respectively. The plane converter also computes line coefficients for each of the edges of the polygon.

Abstract: A content-addressable, first-in/first-out memory (CAM-FIFO), as used to provide a read-modify-write buffer for data between two processes, includes: a Content Addressable Memory (CAM) which stores flag data; a FIFO memory portion for providing data storage; a write/read address counting section for providing write/read addresses of data to be stored in/read from the FIFO; and logic to determine and is used to query data on the queue to determine if the FIFO data should still be sent to the receiving process, or replaced with at least part of the flag data.

Abstract: A state machine controller which can be used for fetching data for a real-time computer image generation system and which provides valid data for each clock interval of a system control clock. The state machine controller can produce a result per clock pulse, schedule new data to be processed before completion of the processing of previous data to prevent bubbles or interruptions in the data pipeline, and can stop and maintain its output if a hold is applied from a later pipeline stage, and can resume one clock operation on the clock pulse when the hold is removed.

Abstract: The total illumination of each pixel to be displayed by a real-time computer image generator, is determined for at least one source illuminating a scene to be displayed, by storing in an observer depth buffer data signals representing those portions of object polygons visible to the observer in each pixel of the display, and storing in a source depth buffer, associated with each of the at least one scene-illuminating light sources, data signals representing illumination intensity received by each polygon pixel viewable from that associated source. A data signal, for each displayable pixel in the observer depth buffer, is generated by combining in non-saturating manner the illumination intensity of each light source impingent upon the equivalent pixel in all of the associated source depth buffers.