Abstract: A video encoder/decoder includes a vector pipeline unit and is configured only once by a processor to encode/decode data in accordance with any one of the JPEG, MPEG1, MPEG2 or MPEG4, H.261 or H.263 compression standards. The configuration data is stored in a configuration register of the video encoder/decoder. An optional ROM stores the configuration data for subsequent reading and loading—by the processor—into the configuration register. The vector pipeline unit includes: a run-length decoder, a binary arithmetic logic unit, a binary multiplier/divider, an accumulator, a barrel shifter, a round/modify unit, a saturate logic unit, a status register and a run-length encoder. Each component of the vector pipeline unit is optionally enabled or disabled. By disabling one or more components of the vector pipeline unit the power consumed by the encoder/decoder is reduced.

Abstract: A technique for digital video processing in a predictive manner is provided. In one embodiment, a method for processing digital video signals for live video applications comprises providing video data that comprise a plurality of frames, identifying a first frame and a second frame in the frame sequences, and processing the information of the first frame and the information of the second frame to determine a quantization step for the second frame. The step of processing the information of the first frame and the information of the second frame further comprises calculating a sigmaSAD value for the second frame, calculating a divisor value for the second frame, and calculating the quantization step for the second frame. In another embodiment, a system for processing digital video signals for live video applications comprises a memory unit within which a computer program is stored. The computer program instructs the system to process digital video in a predicative manner.