Abstract: A mixed-signal in-memory computing sub-cell only requires 9 transistors for 1-bit multiplication. A computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and a common transistor. A MAC array for performing MAC operations, includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. A differential version of the MAC array provides improved computation error tolerance and an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, allowing the computing module to have a reduced area and suffer from fewer computational errors.

Abstract: In one aspect, a time division interleaving band-pass filter can be used in voice activity detection, which operates at different central frequencies in respective intervals of a predetermined period of time. The band-pass filter circuitry includes multiple band-pass filtering channels sharing a common transistor circuit, bias circuit and current mirror circuit. The multiple band-pass filtering channels operate in a time division interleaving manner, which enables the sharing of the common set of band-pass filter circuitry components. Thus, the present invention allows a reduced chip area as the area does not increase proportionally with the number of filtering channels. The invention also mitigates the influence of transistor fabrication variations on the filter's central frequencies.

Abstract: A method for implementing a neural network accelerator using only on-chip memory is provided. The method includes: according to a current neural network model, determining a layer having a minimum value of an output feature map in a neural network (101); determining a quantity of layers of pipeline computing (102); determining a quantity of PEs used for pipeline computing (103); applying for a PE and storing an output feature map of the last layer of pipeline computing in on-chip memory (104), releasing a PE corresponding to a layer at which pipeline computing is completed (105), and repeating the above process at a layer at which computing is to be performed until pipeline computing is completed at all layers of the entire neural network. A neural network accelerator using only on-chip memory is further provided, including a controller, a loading module, a computing array, a post processing module, a storage module, and an on-chip buffer.